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TIMG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xD0 byte (0x0)
mem_usage : registers
protection :

Registers

TRGMR

TRGCNTC

TRGCR

TRGIER

TRGSR

TRGIOR

TRG

TRGGRA

TRGGRB

TRGGRC

TRGGRD


TRGMR

Timer mode register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMR TRGMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRGPWM TRGMDF TRGDFA TRGDFB TRGDFCK TRGELCICE TRGSTART

TRGPWM : PWM mode select
bits : 0 - 0 (1 bit)

TRGMDF : Phase counting mode select
bits : 1 - 2 (2 bit)

TRGDFA : Digital filer function select for TRGIO0 pin
bits : 2 - 4 (3 bit)

TRGDFB : Digital filer function select for TRGIO1 pin
bits : 3 - 6 (4 bit)

TRGDFCK : Digital filter function clock select
bits : 4 - 9 (6 bit)

TRGELCICE : EVENTC input capture request select
bits : 6 - 12 (7 bit)

TRGSTART : Timer count start
bits : 7 - 14 (8 bit)


TRGCNTC

Timer count control register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGCNTC TRGCNTC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CNTEN0 CNTEN1 CNTEN2 CNTEN3 CNTEN4 CNTEN5 CNTEN6 CNTEN7

CNTEN0 : counter enable 0
bits : 0 - 0 (1 bit)

CNTEN1 : counter enable 1
bits : 1 - 2 (2 bit)

CNTEN2 : counter enable 2
bits : 2 - 4 (3 bit)

CNTEN3 : counter enable 3
bits : 3 - 6 (4 bit)

CNTEN4 : counter enable 4
bits : 4 - 8 (5 bit)

CNTEN5 : counter enable 5
bits : 5 - 10 (6 bit)

CNTEN6 : counter enable 6
bits : 6 - 12 (7 bit)

CNTEN7 : counter enable 7
bits : 7 - 14 (8 bit)


TRGCR

Timer control register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGCR TRGCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRGTCK TRGCKEG TRGCCLR

TRGTCK : Count source select
bits : 0 - 2 (3 bit)

TRGCKEG : External clock active edge select
bits : 3 - 7 (5 bit)

TRGCCLR : TRG register clear source select
bits : 5 - 11 (7 bit)


TRGIER

Timer interrupt enable register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGIER TRGIER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRGIMIEA TRGIMIEB TRGUDIE TRGOVIE

TRGIMIEA : Input-capture/compare-match interrupt enable A
bits : 0 - 0 (1 bit)

TRGIMIEB : Input-capture/compare-match interrupt enable B
bits : 1 - 2 (2 bit)

TRGUDIE : Underflow interrupt enable
bits : 2 - 4 (3 bit)

TRGOVIE : Overflow interrupt enable
bits : 3 - 6 (4 bit)


TRGSR

Timer status enable register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGSR TRGSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRGIMFA TRGIMFB TRGUDF TRGOVF TRGDIRF

TRGIMFA : Input-capture/compare-match flag A
bits : 0 - 0 (1 bit)

TRGIMFB : Input-capture/compare-match flag B
bits : 1 - 2 (2 bit)

TRGUDF : Underflow flag
bits : 2 - 4 (3 bit)

TRGOVF : Overflow flag
bits : 3 - 6 (4 bit)

TRGDIRF : Count direction flag
bits : 4 - 8 (5 bit)


TRGIOR

Timer I/O control register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGIOR TRGIOR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRGIOA TRGBUFA TRGIOB TRGBUFB

TRGIOA : TRGGRA mode select and control
bits : 0 - 2 (3 bit)

TRGBUFA : TRGGRC register function select
bits : 3 - 6 (4 bit)

TRGIOB : TRGGRB mode select and control
bits : 4 - 10 (7 bit)

TRGBUFB : TRGGRD register function select
bits : 7 - 14 (8 bit)


TRG

Timer counter register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRG TRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRGGRA

Timer general register %s
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGGRA TRGGRA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRGGRB

Timer general register %s
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGGRB TRGGRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRGGRC

Timer general register %s
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGGRC TRGGRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRGGRD

Timer general register %s
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGGRD TRGGRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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