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TMB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xD0 byte (0x0)
mem_usage : registers
protection :

Registers

TBMR

TBCNTC

TBCR

TBIER

TBSR

TBIOR

TB

TBGRA

TBGRB

TBGRC

TBGRD


TBMR

Timer mode register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBMR TBMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TBPWM TBMDF TBDFA TBDFB TBDFCK TBELCICE TBSTART

TBPWM : PWM mode select
bits : 0 - 0 (1 bit)

TBMDF : Phase counting mode select
bits : 1 - 2 (2 bit)

TBDFA : Digital filer function select for TBIO0 pin
bits : 2 - 4 (3 bit)

TBDFB : Digital filer function select for TBIO1 pin
bits : 3 - 6 (4 bit)

TBDFCK : Digital filter function clock select
bits : 4 - 9 (6 bit)

TBELCICE : EVENTC input capture request select
bits : 6 - 12 (7 bit)

TBSTART : Timer count start
bits : 7 - 14 (8 bit)


TBCNTC

Timer count control register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBCNTC TBCNTC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CNTEN0 CNTEN1 CNTEN2 CNTEN3 CNTEN4 CNTEN5 CNTEN6 CNTEN7

CNTEN0 : counter enable 0
bits : 0 - 0 (1 bit)

CNTEN1 : counter enable 1
bits : 1 - 2 (2 bit)

CNTEN2 : counter enable 2
bits : 2 - 4 (3 bit)

CNTEN3 : counter enable 3
bits : 3 - 6 (4 bit)

CNTEN4 : counter enable 4
bits : 4 - 8 (5 bit)

CNTEN5 : counter enable 5
bits : 5 - 10 (6 bit)

CNTEN6 : counter enable 6
bits : 6 - 12 (7 bit)

CNTEN7 : counter enable 7
bits : 7 - 14 (8 bit)


TBCR

Timer control register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBCR TBCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TBTCK TBCKEG TBCCLR

TBTCK : Count source select
bits : 0 - 2 (3 bit)

TBCKEG : External clock active edge select
bits : 3 - 7 (5 bit)

TBCCLR : TB register clear source select
bits : 5 - 11 (7 bit)


TBIER

Timer interrupt enable register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBIER TBIER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TBIMIEA TBIMIEB TBUDIE TBOVIE

TBIMIEA : Input-capture/compare-match interrupt enable A
bits : 0 - 0 (1 bit)

TBIMIEB : Input-capture/compare-match interrupt enable B
bits : 1 - 2 (2 bit)

TBUDIE : Underflow interrupt enable
bits : 2 - 4 (3 bit)

TBOVIE : Overflow interrupt enable
bits : 3 - 6 (4 bit)


TBSR

Timer status enable register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBSR TBSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TBIMFA TBIMFB TBUDF TBOVF TBDIRF

TBIMFA : Input-capture/compare-match flag A
bits : 0 - 0 (1 bit)

TBIMFB : Input-capture/compare-match flag B
bits : 1 - 2 (2 bit)

TBUDF : Underflow flag
bits : 2 - 4 (3 bit)

TBOVF : Overflow flag
bits : 3 - 6 (4 bit)

TBDIRF : Count direction flag
bits : 4 - 8 (5 bit)


TBIOR

Timer I/O control register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBIOR TBIOR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TBIOA TBBUFA TBIOB TBBUFB

TBIOA : TBGRA mode select and control
bits : 0 - 2 (3 bit)

TBBUFA : TBGRC register function select
bits : 3 - 6 (4 bit)

TBIOB : TBGRB mode select and control
bits : 4 - 10 (7 bit)

TBBUFB : TBGRD register function select
bits : 7 - 14 (8 bit)


TB

Timer counter register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TB TB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TBGRA

Timer general register %s
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBGRA TBGRA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TBGRB

Timer general register %s
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBGRB TBGRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TBGRC

Timer general register %s
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBGRC TBGRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TBGRD

Timer general register %s
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBGRD TBGRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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