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TRD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1200 byte (0x0)
mem_usage : registers
protection :

Registers

TRDELC

TRDCR0

TRDIORA0

OPCTL0

OPDF0

OPDF1

OPEDGE

OPSR

TRDIORC0

TRDSR0

TRDIER0

TRDPOCR0

TRD0

TRDGRA0

TRDGRB0

TRDCR1

TRDIORA1

TRDIORC1

TRDSR1

TRDIER1

TRDPOCR1

TRD1

TRDGRA1

TRDGRB1

TRDSTR

TRDMR

TRDPMR

TRDFCR

TRDOER1

TRDOER2

TRDOCR

TRDDF0

TRDDF1

TRDGRC0

TRDGRD0

TRDGRC1

TRDGRD1


TRDELC

Timer ELC register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDELC TRDELC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ELCICE0 ELCOBE0 ELCICE1 ELCOBE1

ELCICE0 : ELC event input 0 select for timer RD input capture D0
bits : 0 - 0 (1 bit)

ELCOBE0 : ELC event input 0 enable for timer RD output forced cutoff
bits : 1 - 2 (2 bit)

ELCICE1 : ELC event input 1 select for timer RD input capture D1
bits : 4 - 8 (5 bit)

ELCOBE1 : ELC event input 1 enable for timer RD output forced cutoff
bits : 5 - 10 (6 bit)


TRDCR0

Timer control register 0
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDCR0 TRDCR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TCK CKEG CCLR

TCK : Count source select
bits : 0 - 2 (3 bit)

CKEG : External clock edge select
bits : 3 - 7 (5 bit)

CCLR : TRDi counter clear select
bits : 5 - 12 (8 bit)


TRDIORA0

Timer I/O control register A0
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDIORA0 TRDIORA0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IOA IOB

IOA : TRDGRA mode control
bits : 0 - 2 (3 bit)

IOB : TRDGRB mode control
bits : 4 - 10 (7 bit)


OPCTL0

PWMOPA control register 0
address_offset : 0x11F8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPCTL0 OPCTL0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HS_SEL HZ_REL ACT IN_SEL IN_EG HAZAD_SET

HS_SEL : Output forced cutoff release mode selection
bits : 0 - 0 (1 bit)

HZ_REL : Output cutoff release control for software release
bits : 1 - 2 (2 bit)

ACT : Software release timing selection for software release
bits : 2 - 4 (3 bit)

IN_SEL : Cutoff source selection
bits : 3 - 7 (5 bit)

IN_EG : Output forced cutoff and release of edge selection
bits : 5 - 10 (6 bit)

HAZAD_SET : Output cutoff hazard control selection
bits : 6 - 12 (7 bit)


OPDF0

PWMOPA cutoff control register 0
address_offset : 0x11F9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPDF0 OPDF0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DFA0 DFB0 DFC0 DFD0

DFA0 : TRDIOA0 pin output forced cutoff control
bits : 0 - 1 (2 bit)

DFB0 : TRDIOB0 pin output forced cutoff control
bits : 2 - 5 (4 bit)

DFC0 : TRDIOC0 pin output forced cutoff control
bits : 4 - 9 (6 bit)

DFD0 : TRDIOD0 pin output forced cutoff control
bits : 6 - 13 (8 bit)


OPDF1

PWMOPA cutoff control register 1
address_offset : 0x11FA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPDF1 OPDF1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DFA1 DFB1 DFC1 DFD1

DFA1 : TRDIOA1 pin output forced cutoff control
bits : 0 - 1 (2 bit)

DFB1 : TRDIOB1 pin output forced cutoff control
bits : 2 - 5 (4 bit)

DFC1 : TRDIOC1 pin output forced cutoff control
bits : 4 - 9 (6 bit)

DFD1 : TRDIOD1 pin output forced cutoff control
bits : 6 - 13 (8 bit)


OPEDGE

PWMOPA edge selection register
address_offset : 0x11FB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPEDGE OPEDGE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EG

EG : Output forced cutoff release edge selection
bits : 0 - 1 (2 bit)


OPSR

PWMOPA status register
address_offset : 0x11FC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPSR OPSR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HZIF0 HZOF0 HZOF1

HZIF0 : Output cutoff source state
bits : 0 - 0 (1 bit)

HZOF0 : cutoff state
bits : 1 - 2 (2 bit)

HZOF1 : cutoff state
bits : 2 - 4 (3 bit)


TRDIORC0

Timer I/O control register C0
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDIORC0 TRDIORC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IOC IOD

IOC : TRDGRC mode control
bits : 0 - 3 (4 bit)

IOD : TRDGRD mode control
bits : 4 - 11 (8 bit)


TRDSR0

Timer status register 0
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDSR0 TRDSR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IMFA IMFB IMFC IMFD OVF

IMFA : Input capture/compare match flag A
bits : 0 - 0 (1 bit)

IMFB : Input capture/compare match flag B
bits : 1 - 2 (2 bit)

IMFC : Input capture/compare match flag C
bits : 2 - 4 (3 bit)

IMFD : Input capture/compare match flag D
bits : 3 - 6 (4 bit)

OVF : Overflow flag
bits : 4 - 8 (5 bit)


TRDIER0

Timer interrupt enable register 0
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDIER0 TRDIER0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IMIEA IMIEB IMIEC IMIED OVIE

IMIEA : Input capture/compare match interrupt enable A
bits : 0 - 0 (1 bit)

IMIEB : Input capture/compare match interrupt enable B
bits : 1 - 2 (2 bit)

IMIEC : Input capture/compare match interrupt enable C
bits : 2 - 4 (3 bit)

IMIED : Input capture/compare match interrupt enable D
bits : 3 - 6 (4 bit)

OVIE : Overflow/underflow interrupt enable
bits : 4 - 8 (5 bit)


TRDPOCR0

PWM output level control register 0
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDPOCR0 TRDPOCR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 POLB POLC POLD

POLB : PWM output level control B
bits : 0 - 0 (1 bit)

POLC : PWM output level control C
bits : 1 - 2 (2 bit)

POLD : PWM output level control D
bits : 2 - 4 (3 bit)


TRD0

Timer RD counter 0
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRD0 TRD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDGRA0

Timer RD general register A0
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDGRA0 TRDGRA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDGRB0

Timer RD general register B0
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDGRB0 TRDGRB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDCR1

Timer control register 1
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDCR1 TRDCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDIORA1

Timer I/O control register A1
address_offset : 0x21 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDIORA1 TRDIORA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDIORC1

Timer I/O control register C1
address_offset : 0x22 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDIORC1 TRDIORC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDSR1

Timer status register 1
address_offset : 0x23 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDSR1 TRDSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDF

UDF : Underflow flag
bits : 5 - 10 (6 bit)


TRDIER1

Timer interrupt enable register 1
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDIER1 TRDIER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDPOCR1

PWM output level control register 1
address_offset : 0x25 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDPOCR1 TRDPOCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRD1

Timer RD counter 1
address_offset : 0x26 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRD1 TRD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDGRA1

Timer RD general register A1
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDGRA1 TRDGRA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDGRB1

Timer RD general register B1
address_offset : 0x2A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDGRB1 TRDGRB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDSTR

Timer start register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDSTR TRDSTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TSTART0 TSTART1 CSEL0 CSEL1

TSTART0 : TRD0 count start flag
bits : 0 - 0 (1 bit)

TSTART1 : TRD1 count start flag
bits : 1 - 2 (2 bit)

CSEL0 : TRD0 count operation select
bits : 2 - 4 (3 bit)

CSEL1 : TRD1 count operation select
bits : 3 - 6 (4 bit)


TRDMR

Timer mode register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDMR TRDMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRDSYNC TRDBFC0 TRDBFD0 TRDBFC1 TRDBFD1

TRDSYNC : TRDs synchronous
bits : 0 - 0 (1 bit)

TRDBFC0 : TRDGRC0 register function select
bits : 4 - 8 (5 bit)

TRDBFD0 : TRDGRD0 register function select
bits : 5 - 10 (6 bit)

TRDBFC1 : TRDGRC1 register function select
bits : 6 - 12 (7 bit)

TRDBFD1 : TRDGRD1 register function select
bits : 7 - 14 (8 bit)


TRDPMR

PWM function select register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDPMR TRDPMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRDPWMB0 TRDPWMC0 TRDPWMD0 TRDPWMB1 TRDPWMC1 TRDPWMD1

TRDPWMB0 : PWM function of TRDIOB0 select
bits : 0 - 0 (1 bit)

TRDPWMC0 : PWM function of TRDIOC0 select
bits : 1 - 2 (2 bit)

TRDPWMD0 : PWM function of TRDIOD0 select
bits : 2 - 4 (3 bit)

TRDPWMB1 : PWM function of TRDIOB1 select
bits : 4 - 8 (5 bit)

TRDPWMC1 : PWM function of TRDIOC1 select
bits : 5 - 10 (6 bit)

TRDPWMD1 : PWM function of TRDIOD1 select
bits : 6 - 12 (7 bit)


TRDFCR

Timer function control register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDFCR TRDFCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD OLS0 OLS1 STCLK PWM3

CMD : Combination mode select
bits : 0 - 1 (2 bit)

OLS0 : Phase output level select
bits : 2 - 4 (3 bit)

OLS1 : Counter-Phase output level select
bits : 3 - 6 (4 bit)

STCLK : External clock input select
bits : 6 - 12 (7 bit)

PWM3 : PWM3 mode select
bits : 7 - 14 (8 bit)


TRDOER1

Timer output master enable register 1
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDOER1 TRDOER1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EA0 EB0 EC0 ED0 EA1 EB1 EC1 ED1

EA0 : TRDIOA0 output disable
bits : 0 - 0 (1 bit)

EB0 : TRDIOB0 output disable
bits : 1 - 2 (2 bit)

EC0 : TRDIOC0 output disable
bits : 2 - 4 (3 bit)

ED0 : TRDIOD0 output disable
bits : 3 - 6 (4 bit)

EA1 : TRDIOA1 output disable
bits : 4 - 8 (5 bit)

EB1 : TRDIOB1 output disable
bits : 5 - 10 (6 bit)

EC1 : TRDIOC1 output disable
bits : 6 - 12 (7 bit)

ED1 : TRDIOD1 output disable
bits : 7 - 14 (8 bit)


TRDOER2

Timer output master enable register 2
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDOER2 TRDOER2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TRDSHUTS TRDPTO

TRDSHUTS : Forced cutoff flag
bits : 0 - 0 (1 bit)

TRDPTO : INTP0 of output forced cutoff signal input enabled
bits : 7 - 14 (8 bit)


TRDOCR

Timer output control register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDOCR TRDOCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TOA0 TOB0 TOC0 TOD0 TOA1 TOB1 TOC1 TOD1

TOA0 : TRDIOA0 initial output level select
bits : 0 - 0 (1 bit)

TOB0 : TRDIOB0 initial output level select
bits : 1 - 2 (2 bit)

TOC0 : TRDIOC0 initial output level select
bits : 2 - 4 (3 bit)

TOD0 : TRDIOD0 initial output level select
bits : 3 - 6 (4 bit)

TOA1 : TRDIOA1 initial output level select
bits : 4 - 8 (5 bit)

TOB1 : TRDIOB1 initial output level select
bits : 5 - 10 (6 bit)

TOC1 : TRDIOC1 initial output level select
bits : 6 - 12 (7 bit)

TOD1 : TRDIOD1 initial output level select
bits : 7 - 14 (8 bit)


TRDDF0

Digital filter function select register 0
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDDF0 TRDDF0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DFA DFB DFC DFD DFCK

DFA : TRDIOAi pin digital filter function select
bits : 0 - 0 (1 bit)

DFB : TRDIOBi pin digital filter function select
bits : 1 - 2 (2 bit)

DFC : TRDIOCi pin digital filter function select
bits : 2 - 4 (3 bit)

DFD : TRDIODi pin digital filter function select
bits : 3 - 6 (4 bit)

DFCK : Clock select for digital filter function
bits : 6 - 13 (8 bit)


TRDDF1

Digital filter function select register 1
address_offset : 0xB Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDDF1 TRDDF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDGRC0

Timer RD general register C0
address_offset : 0xF8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDGRC0 TRDGRC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDGRD0

Timer RD general register D0
address_offset : 0xFA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDGRD0 TRDGRD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDGRC1

Timer RD general register C1
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDGRC1 TRDGRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRDGRD1

Timer RD general register D1
address_offset : 0xFE Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRDGRD1 TRDGRD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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