\n
address_offset : 0x0 Bytes (0x0)
size : 0x1200 byte (0x0)
mem_usage : registers
protection :
Timer ELC register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELCICE0 : ELC event input 0 select for timer RD input capture D0
bits : 0 - 0 (1 bit)
ELCOBE0 : ELC event input 0 enable for timer RD output forced cutoff
bits : 1 - 2 (2 bit)
ELCICE1 : ELC event input 1 select for timer RD input capture D1
bits : 4 - 8 (5 bit)
ELCOBE1 : ELC event input 1 enable for timer RD output forced cutoff
bits : 5 - 10 (6 bit)
Timer control register 0
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCK : Count source select
bits : 0 - 2 (3 bit)
CKEG : External clock edge select
bits : 3 - 7 (5 bit)
CCLR : TRDi counter clear select
bits : 5 - 12 (8 bit)
Timer I/O control register A0
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOA : TRDGRA mode control
bits : 0 - 2 (3 bit)
IOB : TRDGRB mode control
bits : 4 - 10 (7 bit)
PWMOPA control register 0
address_offset : 0x11F8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HS_SEL : Output forced cutoff release mode selection
bits : 0 - 0 (1 bit)
HZ_REL : Output cutoff release control for software release
bits : 1 - 2 (2 bit)
ACT : Software release timing selection for software release
bits : 2 - 4 (3 bit)
IN_SEL : Cutoff source selection
bits : 3 - 7 (5 bit)
IN_EG : Output forced cutoff and release of edge selection
bits : 5 - 10 (6 bit)
HAZAD_SET : Output cutoff hazard control selection
bits : 6 - 12 (7 bit)
PWMOPA cutoff control register 0
address_offset : 0x11F9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFA0 : TRDIOA0 pin output forced cutoff control
bits : 0 - 1 (2 bit)
DFB0 : TRDIOB0 pin output forced cutoff control
bits : 2 - 5 (4 bit)
DFC0 : TRDIOC0 pin output forced cutoff control
bits : 4 - 9 (6 bit)
DFD0 : TRDIOD0 pin output forced cutoff control
bits : 6 - 13 (8 bit)
PWMOPA cutoff control register 1
address_offset : 0x11FA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFA1 : TRDIOA1 pin output forced cutoff control
bits : 0 - 1 (2 bit)
DFB1 : TRDIOB1 pin output forced cutoff control
bits : 2 - 5 (4 bit)
DFC1 : TRDIOC1 pin output forced cutoff control
bits : 4 - 9 (6 bit)
DFD1 : TRDIOD1 pin output forced cutoff control
bits : 6 - 13 (8 bit)
PWMOPA edge selection register
address_offset : 0x11FB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EG : Output forced cutoff release edge selection
bits : 0 - 1 (2 bit)
PWMOPA status register
address_offset : 0x11FC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HZIF0 : Output cutoff source state
bits : 0 - 0 (1 bit)
HZOF0 : cutoff state
bits : 1 - 2 (2 bit)
HZOF1 : cutoff state
bits : 2 - 4 (3 bit)
Timer I/O control register C0
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOC : TRDGRC mode control
bits : 0 - 3 (4 bit)
IOD : TRDGRD mode control
bits : 4 - 11 (8 bit)
Timer status register 0
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMFA : Input capture/compare match flag A
bits : 0 - 0 (1 bit)
IMFB : Input capture/compare match flag B
bits : 1 - 2 (2 bit)
IMFC : Input capture/compare match flag C
bits : 2 - 4 (3 bit)
IMFD : Input capture/compare match flag D
bits : 3 - 6 (4 bit)
OVF : Overflow flag
bits : 4 - 8 (5 bit)
Timer interrupt enable register 0
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMIEA : Input capture/compare match interrupt enable A
bits : 0 - 0 (1 bit)
IMIEB : Input capture/compare match interrupt enable B
bits : 1 - 2 (2 bit)
IMIEC : Input capture/compare match interrupt enable C
bits : 2 - 4 (3 bit)
IMIED : Input capture/compare match interrupt enable D
bits : 3 - 6 (4 bit)
OVIE : Overflow/underflow interrupt enable
bits : 4 - 8 (5 bit)
PWM output level control register 0
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POLB : PWM output level control B
bits : 0 - 0 (1 bit)
POLC : PWM output level control C
bits : 1 - 2 (2 bit)
POLD : PWM output level control D
bits : 2 - 4 (3 bit)
Timer RD counter 0
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer RD general register A0
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer RD general register B0
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer control register 1
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer I/O control register A1
address_offset : 0x21 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer I/O control register C1
address_offset : 0x22 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer status register 1
address_offset : 0x23 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UDF : Underflow flag
bits : 5 - 10 (6 bit)
Timer interrupt enable register 1
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM output level control register 1
address_offset : 0x25 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer RD counter 1
address_offset : 0x26 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer RD general register A1
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer RD general register B1
address_offset : 0x2A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer start register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTART0 : TRD0 count start flag
bits : 0 - 0 (1 bit)
TSTART1 : TRD1 count start flag
bits : 1 - 2 (2 bit)
CSEL0 : TRD0 count operation select
bits : 2 - 4 (3 bit)
CSEL1 : TRD1 count operation select
bits : 3 - 6 (4 bit)
Timer mode register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRDSYNC : TRDs synchronous
bits : 0 - 0 (1 bit)
TRDBFC0 : TRDGRC0 register function select
bits : 4 - 8 (5 bit)
TRDBFD0 : TRDGRD0 register function select
bits : 5 - 10 (6 bit)
TRDBFC1 : TRDGRC1 register function select
bits : 6 - 12 (7 bit)
TRDBFD1 : TRDGRD1 register function select
bits : 7 - 14 (8 bit)
PWM function select register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRDPWMB0 : PWM function of TRDIOB0 select
bits : 0 - 0 (1 bit)
TRDPWMC0 : PWM function of TRDIOC0 select
bits : 1 - 2 (2 bit)
TRDPWMD0 : PWM function of TRDIOD0 select
bits : 2 - 4 (3 bit)
TRDPWMB1 : PWM function of TRDIOB1 select
bits : 4 - 8 (5 bit)
TRDPWMC1 : PWM function of TRDIOC1 select
bits : 5 - 10 (6 bit)
TRDPWMD1 : PWM function of TRDIOD1 select
bits : 6 - 12 (7 bit)
Timer function control register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Combination mode select
bits : 0 - 1 (2 bit)
OLS0 : Phase output level select
bits : 2 - 4 (3 bit)
OLS1 : Counter-Phase output level select
bits : 3 - 6 (4 bit)
STCLK : External clock input select
bits : 6 - 12 (7 bit)
PWM3 : PWM3 mode select
bits : 7 - 14 (8 bit)
Timer output master enable register 1
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA0 : TRDIOA0 output disable
bits : 0 - 0 (1 bit)
EB0 : TRDIOB0 output disable
bits : 1 - 2 (2 bit)
EC0 : TRDIOC0 output disable
bits : 2 - 4 (3 bit)
ED0 : TRDIOD0 output disable
bits : 3 - 6 (4 bit)
EA1 : TRDIOA1 output disable
bits : 4 - 8 (5 bit)
EB1 : TRDIOB1 output disable
bits : 5 - 10 (6 bit)
EC1 : TRDIOC1 output disable
bits : 6 - 12 (7 bit)
ED1 : TRDIOD1 output disable
bits : 7 - 14 (8 bit)
Timer output master enable register 2
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRDSHUTS : Forced cutoff flag
bits : 0 - 0 (1 bit)
TRDPTO : INTP0 of output forced cutoff signal input enabled
bits : 7 - 14 (8 bit)
Timer output control register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOA0 : TRDIOA0 initial output level select
bits : 0 - 0 (1 bit)
TOB0 : TRDIOB0 initial output level select
bits : 1 - 2 (2 bit)
TOC0 : TRDIOC0 initial output level select
bits : 2 - 4 (3 bit)
TOD0 : TRDIOD0 initial output level select
bits : 3 - 6 (4 bit)
TOA1 : TRDIOA1 initial output level select
bits : 4 - 8 (5 bit)
TOB1 : TRDIOB1 initial output level select
bits : 5 - 10 (6 bit)
TOC1 : TRDIOC1 initial output level select
bits : 6 - 12 (7 bit)
TOD1 : TRDIOD1 initial output level select
bits : 7 - 14 (8 bit)
Digital filter function select register 0
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFA : TRDIOAi pin digital filter function select
bits : 0 - 0 (1 bit)
DFB : TRDIOBi pin digital filter function select
bits : 1 - 2 (2 bit)
DFC : TRDIOCi pin digital filter function select
bits : 2 - 4 (3 bit)
DFD : TRDIODi pin digital filter function select
bits : 3 - 6 (4 bit)
DFCK : Clock select for digital filter function
bits : 6 - 13 (8 bit)
Digital filter function select register 1
address_offset : 0xB Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer RD general register C0
address_offset : 0xF8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer RD general register D0
address_offset : 0xFA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer RD general register C1
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer RD general register D1
address_offset : 0xFE Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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