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TMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

TC

TCBUF

TCCR1

TCCR2

TCSR


TC

Timer counter register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TCBUF

Timer count buffer register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCBUF TCBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TCCR1

Timer control register 1
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCCR1 TCCR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVIE TM_TRIG TRIG_MD_HW TRIG_MD_SW START_MD TCK

OVIE : Enables overflow interrupt
bits : 0 - 0 (1 bit)

TM_TRIG : Selects a hardware start trigger from timer M
bits : 1 - 2 (2 bit)

TRIG_MD_HW : Selects operation in a count mode selected by a trigger from timer M
bits : 2 - 4 (3 bit)

TRIG_MD_SW : Signal for enabling TC counter reset by software
bits : 3 - 6 (4 bit)

START_MD : Selects count start source
bits : 4 - 8 (5 bit)

TCK : Selects count source
bits : 5 - 12 (8 bit)


TCCR2

Timer control register 2
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCCR2 TCCR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TSTART CMP1_TCR

TSTART : counter start
bits : 0 - 0 (1 bit)

CMP1_TCR : Selects operation to be performed when a trigger is generated from comparator 1
bits : 1 - 3 (3 bit)


TCSR

Timer status register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCSR TCSR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TCOVF TCSB

TCOVF : Overflow status of TC counter
bits : 0 - 0 (1 bit)

TCSB : Counter status flag
bits : 1 - 2 (2 bit)



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