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TMM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :

Registers

TMELC

TMCR0

TMIORA0

OPCTL0

OPDF0

OPDF1

OPEDGE

OPSR

TMIORC0

TMSR0

TMIER0

TMPOCR0

TM0

TMGRA0

TMGRB0

TMCR1

TMIORA1

TMIORC1

TMSR1

TMIER1

TMPOCR1

TM1

TMGRA1

TMGRB1

TMSTR

TMMR

TMPMR

TMFCR

TMOER1

TMOER2

TMOCR

TMDF0

TMDF1

TMGRC0

TMGRD0

TMGRC1

TMGRD1


TMELC

Timer ELC register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMELC TMELC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ELCICE0 ELCOBE0 ELCICE1 ELCOBE1

ELCICE0 : ELC event input 0 select for timer M input capture D0
bits : 0 - 0 (1 bit)

ELCOBE0 : ELC event input 0 enable for timer M pulse output forced cutoff
bits : 1 - 2 (2 bit)

ELCICE1 : ELC event input 1 select for timer M input capture D1
bits : 4 - 8 (5 bit)

ELCOBE1 : ELC event input 1 enable for timer M pulse output forced cutoff
bits : 5 - 10 (6 bit)


TMCR0

Timer control register 0
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMCR0 TMCR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TCK CKEG CCLR

TCK : Count source select
bits : 0 - 2 (3 bit)

CKEG : External clock edge select
bits : 3 - 7 (5 bit)

CCLR : TMi counter clear select
bits : 5 - 12 (8 bit)


TMIORA0

Timer I/O control register A0
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMIORA0 TMIORA0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IOA IOB

IOA : TMGRA mode control
bits : 0 - 2 (3 bit)

IOB : TMGRB mode control
bits : 4 - 10 (7 bit)


OPCTL0

PWMOPA control register 0
address_offset : 0x11F8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPCTL0 OPCTL0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HS_SEL HZ_REL ACT IN_SEL IN_EG HAZAD_SET

HS_SEL : Output forced cutoff release mode selection
bits : 0 - 0 (1 bit)

HZ_REL : When software release is selected: Output cutoff release control
bits : 1 - 2 (2 bit)

ACT : When software release is selected: Software release timing selection
bits : 2 - 4 (3 bit)

IN_SEL : Cutoff source selection
bits : 3 - 7 (5 bit)

IN_EG : Output forced cutoff source edge/output forced cutoff release edge selection
bits : 5 - 10 (6 bit)

HAZAD_SET : Output cutoff hazard control selection
bits : 6 - 12 (7 bit)


OPDF0

PWMOPA cutoff control register 0
address_offset : 0x11F9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPDF0 OPDF0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DFA0 DFB0 DFC0 DFD0

DFA0 : TMIOA0 pin output forced cutoff control
bits : 0 - 1 (2 bit)

DFB0 : TMIOB0 pin output forced cutoff control
bits : 2 - 5 (4 bit)

DFC0 : TMIOC0 pin output forced cutoff control
bits : 4 - 9 (6 bit)

DFD0 : TMIOD0 pin output forced cutoff control
bits : 6 - 13 (8 bit)


OPDF1

PWMOPA cutoff control register 1
address_offset : 0x11FA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPDF1 OPDF1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DFA1 DFB1 DFC1 DFD1

DFA1 : TMIOA1 pin output forced cutoff control
bits : 0 - 1 (2 bit)

DFB1 : TMIOB1 pin output forced cutoff control
bits : 2 - 5 (4 bit)

DFC1 : TMIOC1 pin output forced cutoff control
bits : 4 - 9 (6 bit)

DFD1 : TMIOD1 pin output forced cutoff control
bits : 6 - 13 (8 bit)


OPEDGE

PWMOPA edge selection register
address_offset : 0x11FB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPEDGE OPEDGE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EG

EG : Output forced cutoff release edge selection
bits : 0 - 1 (2 bit)


OPSR

PWMOPA status register
address_offset : 0x11FC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPSR OPSR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HZIF0 HZOF0 HZOF1

HZIF0 : Output cutoff source state
bits : 0 - 0 (1 bit)

HZOF0 : cutoff state
bits : 1 - 2 (2 bit)

HZOF1 : cutoff state
bits : 2 - 4 (3 bit)


TMIORC0

Timer I/O control register C0
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMIORC0 TMIORC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IOC IOD

IOC : TMGRC mode control
bits : 0 - 3 (4 bit)

IOD : TMGRD mode control
bits : 4 - 11 (8 bit)


TMSR0

Timer status register 0
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMSR0 TMSR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IMFA IMFB IMFC IMFD OVF

IMFA : Input capture/compare match flag A
bits : 0 - 0 (1 bit)

IMFB : Input capture/compare match flag B
bits : 1 - 2 (2 bit)

IMFC : Input capture/compare match flag C
bits : 2 - 4 (3 bit)

IMFD : Input capture/compare match flag D
bits : 3 - 6 (4 bit)

OVF : Overflow flag
bits : 4 - 8 (5 bit)


TMIER0

Timer interrupt enable register 0
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMIER0 TMIER0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IMIEA IMIEB IMIEC IMIED OVIE

IMIEA : Input capture/compare match interrupt enable A
bits : 0 - 0 (1 bit)

IMIEB : Input capture/compare match interrupt enable B
bits : 1 - 2 (2 bit)

IMIEC : Input capture/compare match interrupt enable C
bits : 2 - 4 (3 bit)

IMIED : Input capture/compare match interrupt enable D
bits : 3 - 6 (4 bit)

OVIE : Overflow/underflow interrupt enable
bits : 4 - 8 (5 bit)


TMPOCR0

PWM output level control register 0
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMPOCR0 TMPOCR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 POLB POLC POLD

POLB : PWM output level control B
bits : 0 - 0 (1 bit)

POLC : PWM output level control C
bits : 1 - 2 (2 bit)

POLD : PWM output level control D
bits : 2 - 4 (3 bit)


TM0

Timer M counter 0
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TM0 TM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMGRA0

Timer M general register A0
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMGRA0 TMGRA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMGRB0

Timer M general register B0
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMGRB0 TMGRB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMCR1

Timer control register 1
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMCR1 TMCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMIORA1

Timer I/O control register A1
address_offset : 0x21 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMIORA1 TMIORA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMIORC1

Timer I/O control register C1
address_offset : 0x22 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMIORC1 TMIORC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMSR1

Timer status register 1
address_offset : 0x23 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMSR1 TMSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UDF

UDF : Underflow flag
bits : 5 - 10 (6 bit)


TMIER1

Timer interrupt enable register 1
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMIER1 TMIER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMPOCR1

PWM output level control register 1
address_offset : 0x25 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMPOCR1 TMPOCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TM1

Timer M counter 1
address_offset : 0x26 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TM1 TM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMGRA1

Timer M general register A1
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMGRA1 TMGRA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMGRB1

Timer M general register B1
address_offset : 0x2A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMGRB1 TMGRB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMSTR

Timer start register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMSTR TMSTR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TSTART0 TSTART1 CSEL0 CSEL1

TSTART0 : TM0 count start flag
bits : 0 - 0 (1 bit)

TSTART1 : TM1 count start flag
bits : 1 - 2 (2 bit)

CSEL0 : TM0 count operation select
bits : 2 - 4 (3 bit)

CSEL1 : TM1 count operation select
bits : 3 - 6 (4 bit)


TMMR

Timer mode register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMMR TMMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TMSYNC TMBFC0 TMBFD0 TMBFC1 TMBFD1

TMSYNC : TMs synchronous
bits : 0 - 0 (1 bit)

TMBFC0 : TMGRC0 register function select
bits : 4 - 8 (5 bit)

TMBFD0 : TMGRD0 register function select
bits : 5 - 10 (6 bit)

TMBFC1 : TMGRC1 register function select
bits : 6 - 12 (7 bit)

TMBFD1 : TMGRD1 register function select
bits : 7 - 14 (8 bit)


TMPMR

PWM function select register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMPMR TMPMR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TMPWMB0 TMPWMC0 TMPWMD0 TMPWMB1 TMPWMC1 TMPWMD1

TMPWMB0 : PWM function of TMIOB0 select
bits : 0 - 0 (1 bit)

TMPWMC0 : PWM function of TMIOC0 select
bits : 1 - 2 (2 bit)

TMPWMD0 : PWM function of TMIOD0 select
bits : 2 - 4 (3 bit)

TMPWMB1 : PWM function of TMIOB1 select
bits : 4 - 8 (5 bit)

TMPWMC1 : PWM function of TMIOC1 select
bits : 5 - 10 (6 bit)

TMPWMD1 : PWM function of TMIOD1 select
bits : 6 - 12 (7 bit)


TMFCR

Timer function control register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMFCR TMFCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD OLS0 OLS1 STCLK PWM3

CMD : Combination mode select
bits : 0 - 1 (2 bit)

OLS0 : Phase output level select
bits : 2 - 4 (3 bit)

OLS1 : Counter-Phase output level select
bits : 3 - 6 (4 bit)

STCLK : External clock input select
bits : 6 - 12 (7 bit)

PWM3 : PWM3 mode select
bits : 7 - 14 (8 bit)


TMOER1

Timer output master enable register 1
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMOER1 TMOER1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EA0 EB0 EC0 ED0 EA1 EB1 EC1 ED1

EA0 : TMIOA0 output disable
bits : 0 - 0 (1 bit)

EB0 : TMIOB0 output disable
bits : 1 - 2 (2 bit)

EC0 : TMIOC0 output disable
bits : 2 - 4 (3 bit)

ED0 : TMIOD0 output disable
bits : 3 - 6 (4 bit)

EA1 : TMIOA1 output disable
bits : 4 - 8 (5 bit)

EB1 : TMIOB1 output disable
bits : 5 - 10 (6 bit)

EC1 : TMIOC1 output disable
bits : 6 - 12 (7 bit)

ED1 : TMIOD1 output disable
bits : 7 - 14 (8 bit)


TMOER2

Timer output master enable register 2
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMOER2 TMOER2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TMSHUTS TMPTO

TMSHUTS : Forced cutoff flag
bits : 0 - 0 (1 bit)

TMPTO : INTP0 pin of pulse output forced cutoff signal input enabled
bits : 7 - 14 (8 bit)


TMOCR

Timer output control register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMOCR TMOCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TOA0 TOB0 TOC0 TOD0 TOA1 TOB1 TOC1 TOD1

TOA0 : TMIOA0 initial output level select
bits : 0 - 0 (1 bit)

TOB0 : TMIOB0 initial output level select
bits : 1 - 2 (2 bit)

TOC0 : TMIOC0 initial output level select
bits : 2 - 4 (3 bit)

TOD0 : TMIOD0 initial output level select
bits : 3 - 6 (4 bit)

TOA1 : TMIOA1 initial output level select
bits : 4 - 8 (5 bit)

TOB1 : TMIOB1 initial output level select
bits : 5 - 10 (6 bit)

TOC1 : TMIOC1 initial output level select
bits : 6 - 12 (7 bit)

TOD1 : TMIOD1 initial output level select
bits : 7 - 14 (8 bit)


TMDF0

Digital filter function select register 0
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMDF0 TMDF0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DFA DFB DFC DFD DFCK

DFA : TMIOAi pin digital filter function select
bits : 0 - 0 (1 bit)

DFB : TMIOBi pin digital filter function select
bits : 1 - 2 (2 bit)

DFC : TMIOCi pin digital filter function select
bits : 2 - 4 (3 bit)

DFD : TMIODi pin digital filter function select
bits : 3 - 6 (4 bit)

DFCK : Clock select for digital filter function
bits : 6 - 13 (8 bit)


TMDF1

Digital filter function select register 1
address_offset : 0xB Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMDF1 TMDF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMGRC0

Timer M general register C0
address_offset : 0xF8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMGRC0 TMGRC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMGRD0

Timer M general register D0
address_offset : 0xFA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMGRD0 TMGRD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMGRC1

Timer M general register C1
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMGRC1 TMGRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TMGRD1

Timer M general register D1
address_offset : 0xFE Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMGRD1 TMGRD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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