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PGA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

PGA0CTL

PGA1CTL


PGA0CTL

PGA 0 control register
address_offset : 0x6 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGA0CTL PGA0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGAVG PVRVS PGAEN

PGAVG : Programmable gain amplifier amplification factor selection
bits : 0 - 2 (3 bit)

PVRVS : GND selection of feedback resistance of the programmable gain amplifier
bits : 3 - 6 (4 bit)

PGAEN : Programmable gain amplifier operation control
bits : 7 - 14 (8 bit)


PGA1CTL

PGA 1 control register
address_offset : 0x7 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGA1CTL PGA1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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