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CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :

Registers

CMC

CSC

HIOTRM

HOCODIV

OSTC

PER0

OSMC

OSTS

CKC

PER1

PER2

SUBCKSEL

MCKC

PLLCR

UPLLCR


CMC

Clock operaton Mode Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMC CMC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 AMPH AMPHS OSCSELS EXCLKS OSCSEL EXCLK

AMPH : Control of X1 clock oscillation frequency
bits : 0 - 0 (1 bit)
access : read-write

AMPHS : Control of XT1 clock oscillation frequency
bits : 1 - 3 (3 bit)
access : read-write

OSCSELS : Sub OSC Select
bits : 4 - 8 (5 bit)
access : read-write

EXCLKS : External Clock input mode
bits : 5 - 10 (6 bit)
access : read-write

OSCSEL : Main OSC Select
bits : 6 - 12 (7 bit)
access : read-write

EXCLK : External Clock input mode
bits : 7 - 14 (8 bit)
access : read-write


CSC

Clock operation Status Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSC CSC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 HIOSTOP XTSTOP MSTOP

HIOSTOP : High-speed on-chip oscillator clock operation control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : START

High-speed on-chip oscillator operating

1 : STOP

High-speed on-chip oscillator stopped

End of enumeration elements list.

XTSTOP : Subsystem clock operation control
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : START

XT1 oscillator operating or External clock from EXCLKS pin is valid

1 : STOP

XT1 oscillator stop or External clock from EXCLKS pin is invalid

End of enumeration elements list.

MSTOP : High-speed system clock operation control
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : START

X1 oscillator operating or External clock from EXCLK pin is valid

1 : STOP

X1 oscillator stop or External clock from EXCLK pin is invalid

End of enumeration elements list.


HIOTRM

High-speed on-chip oscillator trimming register
address_offset : 0x1800 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIOTRM HIOTRM read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

HOCODIV

High-speed on-chip oscillator frequency select register
address_offset : 0x1820 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOCODIV HOCODIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

OSTC

Oscillation stabilization time counter status
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OSTC OSTC read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PER0

Peripheral enable register 0
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER0 PER0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TM40EN TM81EN SCI0EN SCI1EN SCI2EN IICA0EN IICA1EN RTCEN

TM40EN : Control of the TM4 input clock
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

TM81EN : Control of the TM8 input clock
bits : 1 - 2 (2 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

SCI0EN : Control of the SCI0 input clock
bits : 2 - 4 (3 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

SCI1EN : Control of the SCI1 input clock
bits : 3 - 6 (4 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

SCI2EN : Control of the SCI2 input clock
bits : 4 - 8 (5 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

IICA0EN : Control of the IICA0 input clock
bits : 5 - 10 (6 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

IICA1EN : Control of the IICA1 input clock
bits : 6 - 12 (7 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

RTCEN : Control of the RTC input clock
bits : 7 - 14 (8 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.


OSMC

Subsystem clock supply mode control register
address_offset : 0x23 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSMC OSMC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WUTMMCK0 RTCLPC

WUTMMCK0 : Selection of operation clock for real-time clock, 15-bit interval timer
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : fSUB

The subsystem clock is selected as the operation clock for the real-time clock and the 15-bit interval timer.

1 : fIL

The low-speed on-chip oscillator clock is selected as the operation clock for the real-time clock and the 15-bit interval timer.

End of enumeration elements list.

RTCLPC : Setting in DEEPSLEEP mode or SLEEP mode while subsystem clock is selected as CPU clock
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : Enable

Enables supply of subsystem clock to peripheral function

1 : Disable

Stops supply of subsystem clock to peripheral functions other than real-time clock and 15-bit interval timer.

End of enumeration elements list.


OSTS

Oscillation stabilization time select register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSTS OSTS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CKC

System clock control register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKC CKC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MCM0 MCS CSS CLS

MCM0 : Main system clock (fMAIN) operation control
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : fIH

Select the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN)

1 : fMX

Select the high-speed system clock (fMX) as the main system clock (fMAIN)

End of enumeration elements list.

MCS : Status of Main system clock (fMAIN)
bits : 5 - 10 (6 bit)
access : read-only

Enumeration:

0 : fIH

High-speed on-chip oscillator clock (fIH)

1 : fMX

High-speed system clock (fMX)

End of enumeration elements list.

CSS : Selection of CPU/peripheral hardware clock (fCLK)
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

0 : fMAIN

Main system clock (fMAIN)

1 : fSUB

Subsystem clock (fSUB)

End of enumeration elements list.

CLS : Status of CPU/peripheral hardware clock (fCLK)
bits : 7 - 14 (8 bit)
access : read-only

Enumeration:

0 : fMAIN

Main system clock (fMAIN)

1 : fSUB

Subsystem clock (fSUB)

End of enumeration elements list.


PER1

Peripheral enable register 1
address_offset : 0x41A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER1 PER1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADCEN LCDBEN EPWMEN DMAEN IRDAEN PGACMPEN SPIHS0EN SPIHS1EN

ADCEN : Control of the ADC input clock
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

LCDBEN : Control of the LCDB input clock
bits : 1 - 2 (2 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

EPWMEN : Control of the EPWM input clock
bits : 2 - 4 (3 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

DMAEN : Control of the DMA input clock
bits : 3 - 6 (4 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

IRDAEN : Control of the IRDA input clock
bits : 4 - 8 (5 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

PGACMPEN : Control of the PGACMP input clock
bits : 5 - 10 (6 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

SPIHS0EN : Control of the SPIHS0 input clock
bits : 6 - 12 (7 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

SPIHS1EN : Control of the SPIHS1 input clock
bits : 7 - 14 (8 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.


PER2

Peripheral enable register 2
address_offset : 0x41B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER2 PER2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USBEN SSIEN

USBEN : Control of the USB input clock
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.

SSIEN : Control of the SSI input clock
bits : 1 - 2 (2 bit)

Enumeration:

0 : Disabled

Disables input clock supply

1 : Enable

Enables input clock supply

End of enumeration elements list.


SUBCKSEL

Subsystem Clock select register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUBCKSEL SUBCKSEL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SELLOSC

SELLOSC : Select LOSC or SUBOSC
bits : 0 - 0 (1 bit)

Enumeration:

0 : SUBOSC

Select SUBOSC as the SubSystem clock

1 : LOSC

Select LOSC as the SubSystem clock

End of enumeration elements list.


MCKC

Main system clock control register
address_offset : 0x800 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCKC MCKC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CKSELR PDIV CKSTR

CKSELR : Select f(IH) or f(PLL)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : fIH

Select the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN)

1 : PLL

Select the PLL clock (fPLL) as the main system clock (fMAIN)

End of enumeration elements list.

PDIV : PLL frequency select register
bits : 1 - 3 (3 bit)
access : read-write

CKSTR : Status of Main system clock (fMAIN)
bits : 7 - 14 (8 bit)
access : read-only

Enumeration:

0 : fIH

High-speed on-chip oscillator clock (fIH)

1 : fPLL

PLL clock (fPLL)

End of enumeration elements list.


PLLCR

System PLL clock control register
address_offset : 0x802 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCR PLLCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PLLON PLLM PLLD PLLSRSEL

PLLON : PLL operation control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : PLL STOP

PLL is stopped

1 : PLL ON

PLL is operating

End of enumeration elements list.

PLLM : PLL frequency multiplication factor select
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : X12

PLL multiplication factor is 12

1 : X16

PLL multiplication factor is 16

End of enumeration elements list.

PLLD : PLL frequency division ratio select
bits : 2 - 5 (4 bit)
access : read-write

PLLSRSEL : PLL input clock source select
bits : 7 - 14 (8 bit)
access : read-only

Enumeration:

0 : fIH

Select the high-speed on-chip oscillator clock (fIH) as PLL input source

1 : fMX

Select external main system clock f(MX) as PLL input source

End of enumeration elements list.


UPLLCR

USB-dedicated system PLL clock control register
address_offset : 0x803 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UPLLCR UPLLCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 UPLLON UPLLM UPLLD UPLLSRSEL

UPLLON : USB-dedicated PLL operation control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : UPLL STOP

UPLL is stopped

1 : UPLL ON

UPLL is operating

End of enumeration elements list.

UPLLM : USB-dedicated PLL frequency multiplication factor select
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : X12

UPLL multiplication factor is 12

1 : X16

UPLL multiplication factor is 16

End of enumeration elements list.

UPLLD : USB-dedicated PLL frequency division ratio select
bits : 2 - 5 (4 bit)
access : read-write

UPLLSRSEL : USB-dedicated PLL input clock source select
bits : 7 - 14 (8 bit)
access : read-only

Enumeration:

0 : fIH

Select the high-speed on-chip oscillator clock (fIH) as UPLL input source

1 : fMX

Select external main system clock f(MX) as UPLL input source

End of enumeration elements list.



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