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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

ADM0

ADTES

ADNDIS

ADSMPWAIT

ADFLG

PGA0SH

ADM1

ADM2

ADTRG

ADS

ADLL

ADUL

ADNSMP

ADCR

ADCRH


ADM0

A/D mode register 0
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADM0 ADM0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADCE FR ADCS

ADCE : A/D enable
bits : 0 - 0 (1 bit)

FR : A/D conversion clock (fAD) select
bits : 3 - 8 (6 bit)

ADCS : A/D conversion operation control
bits : 7 - 14 (8 bit)


ADTES

A/D test register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADTES ADTES read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

ADNDIS

A/D charge/discharge control register
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADNDIS ADNDIS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

ADSMPWAIT

A/D sampling wait control register
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADSMPWAIT ADSMPWAIT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

ADFLG

A/D flag register
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADFLG ADFLG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

PGA0SH

PGA 0 sample and hold function register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGA0SH PGA0SH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGA0SH PGA0SHEN

PGA0SH : Sample and hold time selection
bits : 0 - 9 (10 bit)

PGA0SHEN : Sample and hold function enable control
bits : 15 - 30 (16 bit)


ADM1

A/D mode register 1
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADM1 ADM1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADMODE ADSCM ADMD

ADMODE : A/D mode select
bits : 0 - 1 (2 bit)

ADSCM : A/D conversion mode
bits : 3 - 6 (4 bit)

Enumeration:

0 : Sequential

Sequential conversion mode

1 : OneShot

One-shot conversion mode

End of enumeration elements list.

ADMD : A/D conversion channel select mode
bits : 7 - 14 (8 bit)

Enumeration:

0 : Select

Select mode

1 : Scan

Scan mode

End of enumeration elements list.


ADM2

A/D mode register 2
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADM2 ADM2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHRDE ADRCK ADREFM ADREFP

CHRDE : output CH number in A/D conversion result in Scan mode
bits : 1 - 2 (2 bit)

ADRCK : the upper limit and lower limit conversion result values
bits : 3 - 6 (4 bit)

ADREFM : Selection of the - side reference voltage of A/D converter
bits : 5 - 10 (6 bit)

Enumeration:

0 : VSS

Supplied from VSS

1 : AVREFM

Supplied from AVREFM

End of enumeration elements list.

ADREFP : Selection of the + side reference voltage of A/D converter
bits : 6 - 13 (8 bit)

Enumeration:

0b00 : VDD

Supplied from VDD

0b01 : AVREFP0

Supplied from AVREFP

0b10 : AVREFP1

Supplied from inside AVREF of A/D

End of enumeration elements list.


ADTRG

A/D mode register 2
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADTRG ADTRG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADTRS ADTMD

ADTRS : A/D hard trigger select
bits : 0 - 1 (2 bit)

ADTMD : A/D conversion trigger mode
bits : 6 - 13 (8 bit)


ADS

Analog input channel specification register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADS ADS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

ADLL

Conversion result comparison lower limit setting register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADLL ADLL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

ADUL

Conversion result comparison upper limit setting register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADUL ADUL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

ADNSMP

A/D sampling time control register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADNSMP ADNSMP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

ADCR

12-bit A/D conversion result register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADCR ADCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADCRH

Higher 8-bit A/D conversion result register
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : ADCR
reset_Mask : 0x0

ADCRH ADCRH read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


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