SCI0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

add a new register to this peripheral

SSR00

SE0

SDR00

SIO00

TXD0

SDR01

SIO01

RXD0

SS0

ST0

SPS0

SO0

SOE0

SSR01

SOL0

SIR00

SIR01

SMR00

SMR01

SCR00

SCR01


SSR00

Serial status register mn
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSR00 SSR00 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF PEF FEF BFF TSF

OVF : Overrun error detection flag of channel n
bits : 0 - 0 (1 bit)

PEF : Parity error detection flag of channel n
bits : 1 - 2 (2 bit)

FEF : Framing error detection flag of channel n
bits : 2 - 4 (3 bit)

BFF : Buffer register status indication flag of channel n
bits : 5 - 10 (6 bit)

TSF : Communication status indication flag of channel n
bits : 6 - 12 (7 bit)


SE0

Serial channel enable status register m
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SE0 SE0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SE00 SE01

SE00 : Indication of operation enable/stop status of channel 0
bits : 0 - 0 (1 bit)

SE01 : Indication of operation enable/stop status of channel 1
bits : 1 - 2 (2 bit)


SDR00

Serial data register 0%s
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDR00 SDR00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SIO00

SPI data register
address_offset : 0x110 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR00
reset_Mask : 0x0

SIO00 SIO00 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TXD0

UART transmit data register
address_offset : 0x110 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR00
reset_Mask : 0x0

TXD0 TXD0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SDR01

Serial data register 0%s
address_offset : 0x112 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDR01 SDR01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SIO01

SPI data register
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR01
reset_Mask : 0x0

SIO01 SIO01 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

RXD0

UART receive data register
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR01
reset_Mask : 0x0

RXD0 RXD0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SS0

Serial channel start register 0
address_offset : 0x12 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SS0 SS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS00 SS01

SS00 : Operation start trigger of channel 0
bits : 0 - 0 (1 bit)

SS01 : Operation start trigger of channel 1
bits : 1 - 2 (2 bit)


ST0

Serial channel stop register 0
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ST0 ST0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST00 ST01

ST00 : Operation stop trigger of channel 0
bits : 0 - 0 (1 bit)

ST01 : Operation stop trigger of channel 1
bits : 1 - 2 (2 bit)


SPS0

Serial clock select register 0
address_offset : 0x16 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPS0 SPS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRS00 PRS01

PRS00 : Prescaler 0
bits : 0 - 3 (4 bit)

PRS01 : Prescaler 1
bits : 4 - 11 (8 bit)


SO0

Serial output register 0
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SO0 SO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SO00 SO01 CKO00 CKO01

SO00 : Serial data output of channel 0
bits : 0 - 0 (1 bit)

SO01 : Serial data output of channel 1
bits : 1 - 2 (2 bit)

CKO00 : Serial clock output of channel 0
bits : 8 - 16 (9 bit)

CKO01 : Serial clock output of channel 1
bits : 9 - 18 (10 bit)


SOE0

Serial output enable register 0
address_offset : 0x1A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOE0 SOE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOE00 SOE01

SOE00 : Serial output enable of channel 0
bits : 0 - 0 (1 bit)

SOE01 : Serial output enable of channel 1
bits : 1 - 2 (2 bit)


SSR01

Serial status register mn
address_offset : 0x2 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR01 SSR01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SOL0

Serial output level register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOL0 SOL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOL00

SOL00 : Selects inversion of the level of the transmit data of channel n in UART mode
bits : 0 - 0 (1 bit)


SIR00

Serial flag clear trigger register mn
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIR00 SIR00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVCT PECT FECT

OVCT : Clear trigger of overrun error flag of channel n
bits : 0 - 0 (1 bit)

PECT : Clear trigger of parity error flag of channel n
bits : 1 - 2 (2 bit)

FECT : Clear trigger of framing error flag of channel n
bits : 2 - 4 (3 bit)


SIR01

Serial flag clear trigger register mn
address_offset : 0x6 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIR01 SIR01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SMR00

Serial mode register mn
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR00 SMR00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD SIS STS CCS CKS

MD : Setting of operation mode of channel n
bits : 0 - 2 (3 bit)

SIS : Controls inversion of level of receive data of channel n in UART mode
bits : 6 - 12 (7 bit)

STS : Selection of start trigger source
bits : 8 - 16 (9 bit)

CCS : Selection of transfer clock (fTCLK) of channel n
bits : 14 - 28 (15 bit)

CKS : Selection of operation clock (fMCK) of channel n
bits : 15 - 30 (16 bit)


SMR01

Serial mode register mn
address_offset : 0xA Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR01 SMR01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCR00

Serial communication operation setting register mn
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR00 SCR00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLS SLC DIR PTC EOC CKP DAP RXE TXE

DLS : Setting of data length in SPI and UART modes
bits : 0 - 3 (4 bit)

SLC : Setting of stop bit in UART mode
bits : 4 - 9 (6 bit)

DIR : Selection of data transfer sequence in SPI and UART modes
bits : 7 - 14 (8 bit)

PTC : Setting of parity bit in UART mode
bits : 8 - 17 (10 bit)

EOC : Mask control of error interrupt signal (INTSREx (x = 0 to 2))
bits : 10 - 20 (11 bit)

CKP : Selection of clock phase in SPI mode
bits : 12 - 24 (13 bit)

DAP : Selection of data phase in SPI mode
bits : 13 - 26 (14 bit)

RXE : Reception enable
bits : 14 - 28 (15 bit)

TXE : Transmission enable
bits : 15 - 30 (16 bit)


SCR01

Serial communication operation setting register mn
address_offset : 0xE Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR01 SCR01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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