SCI1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

add a new register to this peripheral

SSR10

SE1

SDR10

SIO10

TXD1

SDR11

SIO11

RXD1

SS1

ST1

SPS1

SO1

SOE1

SSR11

SOL1

SIR10

SIR11

SMR10

SMR11

SCR10

SCR11


SSR10

Serial status register mn
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSR10 SSR10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF PEF FEF BFF TSF

OVF : Overrun error detection flag of channel n
bits : 0 - 0 (1 bit)

PEF : Parity error detection flag of channel n
bits : 1 - 2 (2 bit)

FEF : Framing error detection flag of channel n
bits : 2 - 4 (3 bit)

BFF : Buffer register status indication flag of channel n
bits : 5 - 10 (6 bit)

TSF : Communication status indication flag of channel n
bits : 6 - 12 (7 bit)


SE1

Serial channel enable status register 1
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SE1 SE1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SE10 SE11

SE10 : Indication of operation enable/stop status of channel 0
bits : 0 - 0 (1 bit)

SE11 : Indication of operation enable/stop status of channel 1
bits : 1 - 2 (2 bit)


SDR10

Serial data register 1%s
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDR10 SDR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SIO10

SPI data register
address_offset : 0x110 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR10
reset_Mask : 0x0

SIO10 SIO10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TXD1

UART transmit data register
address_offset : 0x110 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR10
reset_Mask : 0x0

TXD1 TXD1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SDR11

Serial data register 1%s
address_offset : 0x112 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDR11 SDR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SIO11

SPI data register
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR11
reset_Mask : 0x0

SIO11 SIO11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

RXD1

UART receive data register
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR11
reset_Mask : 0x0

RXD1 RXD1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SS1

Serial channel start register 1
address_offset : 0x12 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SS1 SS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS10 SS11

SS10 : Operation start trigger of channel 0
bits : 0 - 0 (1 bit)

SS11 : Operation start trigger of channel 1
bits : 1 - 2 (2 bit)


ST1

Serial channel stop register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ST1 ST1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST10 ST11

ST10 : Operation stop trigger of channel 0
bits : 0 - 0 (1 bit)

ST11 : Operation stop trigger of channel 1
bits : 1 - 2 (2 bit)


SPS1

Serial clock select register 1
address_offset : 0x16 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPS1 SPS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRS10 PRS11

PRS10 : Prescaler 0
bits : 0 - 3 (4 bit)

PRS11 : Prescaler 1
bits : 4 - 11 (8 bit)


SO1

Serial output register 1
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SO1 SO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SO10 SO11 CKO10 CKO11

SO10 : Serial data output of channel 0
bits : 0 - 0 (1 bit)

SO11 : Serial data output of channel 1
bits : 1 - 2 (2 bit)

CKO10 : Serial clock output of channel 0
bits : 8 - 16 (9 bit)

CKO11 : Serial clock output of channel 1
bits : 9 - 18 (10 bit)


SOE1

Serial output enable register 1
address_offset : 0x1A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOE1 SOE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOE10 SOE11

SOE10 : Serial output enable of channel 0
bits : 0 - 0 (1 bit)

SOE11 : Serial output enable of channel 1
bits : 1 - 2 (2 bit)


SSR11

Serial status register mn
address_offset : 0x2 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR11 SSR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SOL1

Serial output level register 1
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOL1 SOL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOL10

SOL10 : Selects inversion of the level of the transmit data of channel n in UART mode
bits : 0 - 0 (1 bit)


SIR10

Serial flag clear trigger register mn
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIR10 SIR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVCT PECT FECT

OVCT : Clear trigger of overrun error flag of channel n
bits : 0 - 0 (1 bit)

PECT : Clear trigger of parity error flag of channel n
bits : 1 - 2 (2 bit)

FECT : Clear trigger of framing error flag of channel n
bits : 2 - 4 (3 bit)


SIR11

Serial flag clear trigger register mn
address_offset : 0x6 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIR11 SIR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SMR10

Serial mode register mn
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR10 SMR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD SIS STS CCS CKS

MD : Setting of operation mode of channel n
bits : 0 - 2 (3 bit)

SIS : Controls inversion of level of receive data of channel n in UART mode
bits : 6 - 12 (7 bit)

STS : Selection of start trigger source
bits : 8 - 16 (9 bit)

CCS : Selection of transfer clock (fTCLK) of channel n
bits : 14 - 28 (15 bit)

CKS : Selection of operation clock (fMCK) of channel n
bits : 15 - 30 (16 bit)


SMR11

Serial mode register mn
address_offset : 0xA Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR11 SMR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCR10

Serial communication operation setting register mn
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR10 SCR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLS SLC DIR PTC EOC CKP DAP RXE TXE

DLS : Setting of data length in SPI and UART modes
bits : 0 - 1 (2 bit)

SLC : Setting of stop bit in UART mode
bits : 4 - 9 (6 bit)

DIR : Selection of data transfer sequence in SPI and UART modes
bits : 7 - 14 (8 bit)

PTC : Setting of parity bit in UART mode
bits : 8 - 17 (10 bit)

EOC : Mask control of error interrupt signal (INTSREx (x = 0 to 2))
bits : 10 - 20 (11 bit)

CKP : Selection of clock phase in SPI mode
bits : 12 - 24 (13 bit)

DAP : Selection of data phase in SPI mode
bits : 13 - 26 (14 bit)

RXE : Reception enable
bits : 14 - 28 (15 bit)

TXE : Transmission enable
bits : 15 - 30 (16 bit)


SCR11

Serial communication operation setting register mn
address_offset : 0xE Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR11 SCR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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