SCI1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

add a new register to this peripheral

SSR20

SE2

SDR20

SIO20

TXD2

SDR21

SIO21

RXD2

SS2

ST2

SPS2

SO2

SOE2

SSR21

SOL2

SIR20

SIR21

SMR20

SMR21

SCR20

SCR21


SSR20

Serial status register mn
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSR20 SSR20 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF PEF FEF BFF TSF

OVF : Overrun error detection flag of channel n
bits : 0 - 0 (1 bit)

PEF : Parity error detection flag of channel n
bits : 1 - 2 (2 bit)

FEF : Framing error detection flag of channel n
bits : 2 - 4 (3 bit)

BFF : Buffer register status indication flag of channel n
bits : 5 - 10 (6 bit)

TSF : Communication status indication flag of channel n
bits : 6 - 12 (7 bit)


SE2

Serial channel enable status register 2
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SE2 SE2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SE20 SE21

SE20 : Indication of operation enable/stop status of channel 0
bits : 0 - 0 (1 bit)

SE21 : Indication of operation enable/stop status of channel 1
bits : 1 - 2 (2 bit)


SDR20

Serial data register 2%s
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDR20 SDR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SIO20

SPI data register
address_offset : 0x110 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR20
reset_Mask : 0x0

SIO20 SIO20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TXD2

UART transmit data register
address_offset : 0x110 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR20
reset_Mask : 0x0

TXD2 TXD2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SDR21

Serial data register 2%s
address_offset : 0x112 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDR21 SDR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SIO21

SPI data register
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR21
reset_Mask : 0x0

SIO21 SIO21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

RXD2

UART receive data register
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : SDR21
reset_Mask : 0x0

RXD2 RXD2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

SS2

Serial channel start register 2
address_offset : 0x12 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SS2 SS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS20 SS21

SS20 : Operation start trigger of channel 0
bits : 0 - 0 (1 bit)

SS21 : Operation start trigger of channel 1
bits : 1 - 2 (2 bit)


ST2

Serial channel stop register 2
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ST2 ST2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST20 ST21

ST20 : Operation stop trigger of channel 0
bits : 0 - 0 (1 bit)

ST21 : Operation stop trigger of channel 1
bits : 1 - 2 (2 bit)


SPS2

Serial clock select register 0
address_offset : 0x16 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPS2 SPS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRS20 PRS21

PRS20 : Prescaler 0
bits : 0 - 3 (4 bit)

PRS21 : Prescaler 1
bits : 4 - 11 (8 bit)


SO2

Serial output register 0
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SO2 SO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SO20 SO21 CKO20 CKO11

SO20 : Serial data output of channel 0
bits : 0 - 0 (1 bit)

SO21 : Serial data output of channel 1
bits : 1 - 2 (2 bit)

CKO20 : Serial clock output of channel 0
bits : 8 - 16 (9 bit)

CKO11 : Serial clock output of channel 1
bits : 9 - 18 (10 bit)


SOE2

Serial output enable register 2
address_offset : 0x1A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOE2 SOE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOE20 SOE21

SOE20 : Serial output enable of channel 0
bits : 0 - 0 (1 bit)

SOE21 : Serial output enable of channel 1
bits : 1 - 2 (2 bit)


SSR21

Serial status register mn
address_offset : 0x2 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSR21 SSR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SOL2

Serial output level register 2
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOL2 SOL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOL20

SOL20 : Selects inversion of the level of the transmit data of channel n in UART mode
bits : 0 - 0 (1 bit)


SIR20

Serial flag clear trigger register mn
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIR20 SIR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVCT PECT FECT

OVCT : Clear trigger of overrun error flag of channel n
bits : 0 - 0 (1 bit)

PECT : Clear trigger of parity error flag of channel n
bits : 1 - 2 (2 bit)

FECT : Clear trigger of framing error flag of channel n
bits : 2 - 4 (3 bit)


SIR21

Serial flag clear trigger register mn
address_offset : 0x6 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIR21 SIR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SMR20

Serial mode register mn
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR20 SMR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD SIS STS CCS CKS

MD : Setting of operation mode of channel n
bits : 0 - 2 (3 bit)

SIS : Controls inversion of level of receive data of channel n in UART mode
bits : 6 - 12 (7 bit)

STS : Selection of start trigger source
bits : 8 - 16 (9 bit)

CCS : Selection of transfer clock (fTCLK) of channel n
bits : 14 - 28 (15 bit)

CKS : Selection of operation clock (fMCK) of channel n
bits : 15 - 30 (16 bit)


SMR21

Serial mode register mn
address_offset : 0xA Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMR21 SMR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCR20

Serial communication operation setting register mn
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR20 SCR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLS SLC DIR PTC EOC CKP DAP RXE TXE

DLS : Setting of data length in SPI and UART modes
bits : 0 - 1 (2 bit)

SLC : Setting of stop bit in UART mode
bits : 4 - 9 (6 bit)

DIR : Selection of data transfer sequence in SPI and UART modes
bits : 7 - 14 (8 bit)

PTC : Setting of parity bit in UART mode
bits : 8 - 17 (10 bit)

EOC : Mask control of error interrupt signal (INTSREx (x = 0 to 2))
bits : 10 - 20 (11 bit)

CKP : Selection of clock phase in SPI mode
bits : 12 - 24 (13 bit)

DAP : Selection of data phase in SPI mode
bits : 13 - 26 (14 bit)

RXE : Reception enable
bits : 14 - 28 (15 bit)

TXE : Transmission enable
bits : 15 - 30 (16 bit)


SCR21

Serial communication operation setting register mn
address_offset : 0xE Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR21 SCR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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