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SPIHS1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

SPIM1

SPIS1

SPIC1

SDRO1

SDRI1


SPIM1

SPI mode control register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPIM1 SPIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RECMD DLS INTMD DIR NSSE TRMD SPIE

RECMD : Receive mode selection
bits : 1 - 2 (2 bit)

DLS : data length control
bits : 2 - 4 (3 bit)

INTMD : interrupt source select
bits : 3 - 6 (4 bit)

DIR : MSB of LSB mode select
bits : 4 - 8 (5 bit)

NSSE : NSS pin enable
bits : 5 - 10 (6 bit)

TRMD : Transfer and Receive mode
bits : 6 - 12 (7 bit)

SPIE : SPI operation enable
bits : 7 - 14 (8 bit)


SPIS1

SPI status register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPIS1 SPIS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPTF SDRIF

SPTF : SPI transmission status flag
bits : 0 - 0 (1 bit)

SDRIF : Receive buffer non-empty flag
bits : 1 - 2 (2 bit)


SPIC1

SPI control register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPIC1 SPIC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKS DAP CKP

CKS : Operation clock control
bits : 0 - 2 (3 bit)
access : read-write

DAP : Selection of data phase for SPI
bits : 3 - 6 (4 bit)
access : read-write

CKP : Selection of clock phase for SPI
bits : 4 - 8 (5 bit)
access : read-write


SDRO1

Data buffer of transmission
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRO1 SDRO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SDRI1

Data buffer of reception
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDRI1 SDRI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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