IICCTL00

IICCTL01

IICA0

IICS0

IICF0

IICWL0

IICWH0

SVA0

SPT : Stop condition trigger
bits : 0 - 0 (1 bit)

STT : Start condition trigger
bits : 1 - 2 (2 bit)

ACKE : Acknowledgment control
bits : 2 - 4 (3 bit)

WTIM : Control of wait and interrupt request generation
bits : 3 - 6 (4 bit)

SPIE : Enable generation of interrupt request when stop condition is detected
bits : 4 - 8 (5 bit)

WREL : Wait cancellation
bits : 5 - 10 (6 bit)

LREL : Exit from communications
bits : 6 - 12 (7 bit)

IICE : I2C operation enable
bits : 7 - 14 (8 bit)

PRS : Operation clock (fMCK) contro
bits : 0 - 0 (1 bit)
access : read-write

DFC : Digital filter operation control
bits : 2 - 4 (3 bit)
access : read-write

SMC : Operation mode switching
bits : 3 - 6 (4 bit)
access : read-write

DAD : Detection of SDAAn pin level (valid only when IICEn = 1)
bits : 4 - 8 (5 bit)
access : read-only

CLD : Detection of SCLAn pin level (valid only when IICEn = 1)
bits : 5 - 10 (6 bit)
access : read-only

WUP : Control of address match wakeup
bits : 7 - 14 (8 bit)
access : read-write

SPD : Detection of stop condition
bits : 0 - 0 (1 bit)

STD : Detection of start condition
bits : 1 - 2 (2 bit)

ACKD : Detection of acknowledge (ACK)
bits : 2 - 4 (3 bit)

TRC : Detection of transmit/receive status
bits : 3 - 6 (4 bit)

COI : Detection of matching addresses
bits : 4 - 8 (5 bit)

EXC : Detection of extension code reception
bits : 5 - 10 (6 bit)

ALD : Detection of arbitration loss
bits : 6 - 12 (7 bit)

MSTS : Master status check flag
bits : 7 - 14 (8 bit)

IICRSV : Communication reservation function disable bit
bits : 0 - 0 (1 bit)
access : read-write

STCEN : Initial start enable trigger
bits : 1 - 2 (2 bit)
access : read-write

IICBSY : I2C bus status flag
bits : 6 - 12 (7 bit)
access : read-only

STCF : STT clear flag
bits : 7 - 14 (8 bit)
access : read-only