\n

IICA0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

IICCTL00

IICCTL01

IICA0

IICS0

IICF0

IICWL0

IICWH0

SVA0


IICCTL00

IICA0 control register 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICCTL00 IICCTL00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPT STT ACKE WTIM SPIE WREL LREL IICE

SPT : Stop condition trigger
bits : 0 - 0 (1 bit)

STT : Start condition trigger
bits : 1 - 2 (2 bit)

ACKE : Acknowledgment control
bits : 2 - 4 (3 bit)

WTIM : Control of wait and interrupt request generation
bits : 3 - 6 (4 bit)

SPIE : Enable generation of interrupt request when stop condition is detected
bits : 4 - 8 (5 bit)

WREL : Wait cancellation
bits : 5 - 10 (6 bit)

LREL : Exit from communications
bits : 6 - 12 (7 bit)

IICE : I2C operation enable
bits : 7 - 14 (8 bit)


IICCTL01

IICA0 control register 1
address_offset : 0x1 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICCTL01 IICCTL01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRS DFC SMC DAD CLD WUP

PRS : Operation clock (fMCK) contro
bits : 0 - 0 (1 bit)
access : read-write

DFC : Digital filter operation control
bits : 2 - 4 (3 bit)
access : read-write

SMC : Operation mode switching
bits : 3 - 6 (4 bit)
access : read-write

DAD : Detection of SDAAn pin level (valid only when IICEn = 1)
bits : 4 - 8 (5 bit)
access : read-only

CLD : Detection of SCLAn pin level (valid only when IICEn = 1)
bits : 5 - 10 (6 bit)
access : read-only

WUP : Control of address match wakeup
bits : 7 - 14 (8 bit)
access : read-write


IICA0

IICA0 shift register
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICA0 IICA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IICS0

IICA0 status register
address_offset : 0x121 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IICS0 IICS0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPD STD ACKD TRC COI EXC ALD MSTS

SPD : Detection of stop condition
bits : 0 - 0 (1 bit)

STD : Detection of start condition
bits : 1 - 2 (2 bit)

ACKD : Detection of acknowledge (ACK)
bits : 2 - 4 (3 bit)

TRC : Detection of transmit/receive status
bits : 3 - 6 (4 bit)

COI : Detection of matching addresses
bits : 4 - 8 (5 bit)

EXC : Detection of extension code reception
bits : 5 - 10 (6 bit)

ALD : Detection of arbitration loss
bits : 6 - 12 (7 bit)

MSTS : Master status check flag
bits : 7 - 14 (8 bit)


IICF0

IICA0 flag register
address_offset : 0x122 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICF0 IICF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IICRSV STCEN IICBSY STCF

IICRSV : Communication reservation function disable bit
bits : 0 - 0 (1 bit)
access : read-write

STCEN : Initial start enable trigger
bits : 1 - 2 (2 bit)
access : read-write

IICBSY : I2C bus status flag
bits : 6 - 12 (7 bit)
access : read-only

STCF : STT clear flag
bits : 7 - 14 (8 bit)
access : read-only


IICWL0

IICA0 low-level width setting register
address_offset : 0x2 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICWL0 IICWL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IICWH0

IICA0 high-level width setting register
address_offset : 0x3 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IICWH0 IICWH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SVA0

Slave address register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SVA0 SVA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.