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DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

DMAEN0

DMAEN1

DMAIF0

DMAIF1

DMAIF2

DMAIF3

DMAIF4

DMAEN2

DMAEN3

DMAEN4

DMABAR

IFPRCR


DMAEN0

DMA activation enable register %s
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAEN0 DMAEN0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMAEN1

DMA activation enable register %s
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAEN1 DMAEN1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMAIF0

DMA Trigger enable register %s
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAIF0 DMAIF0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMAIF1

DMA Trigger enable register %s
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAIF1 DMAIF1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMAIF2

DMA Trigger enable register %s
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAIF2 DMAIF2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMAIF3

DMA Trigger enable register %s
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAIF3 DMAIF3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMAIF4

DMA Trigger enable register %s
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAIF4 DMAIF4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMAEN2

DMA activation enable register %s
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAEN2 DMAEN2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMAEN3

DMA activation enable register %s
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAEN3 DMAEN3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMAEN4

DMA activation enable register %s
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAEN4 DMAEN4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

DMABAR

DMA base address register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMABAR DMABAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IFPRCR

DMA Trigger Protect register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFPRCR IFPRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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