\n

MISC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

NFEN0

NFEN1

NFEN2

ISC

TIOS0

TIOS1

RTCCL


NFEN0

Noise filter enable register 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NFEN0 NFEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNFEN00 SNFEN10 SNFEN20

SNFEN00 : Enable noise filter of RxD0
bits : 0 - 0 (1 bit)

SNFEN10 : Enable noise filter of RxD1
bits : 2 - 4 (3 bit)

SNFEN20 : Enable noise filter of RxD2
bits : 4 - 8 (5 bit)


NFEN1

Noise filter enable register 1
address_offset : 0x1 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NFEN1 NFEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TNFEN00 TNFEN01 TNFEN02 TNFEN03

TNFEN00 : Enable noise filter of TI00
bits : 0 - 0 (1 bit)

TNFEN01 : Enable noise filter of TI01
bits : 1 - 2 (2 bit)

TNFEN02 : Enable noise filter of TI02
bits : 2 - 4 (3 bit)

TNFEN03 : Enable noise filter of TI03
bits : 3 - 6 (4 bit)


NFEN2

Noise filter enable register 2
address_offset : 0x2 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NFEN2 NFEN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TNFEN10 TNFEN11 TNFEN12 TNFEN13 TNFEN14 TNFEN15 TNFEN16 TNFEN17

TNFEN10 : Enable noise filter of TI10
bits : 0 - 0 (1 bit)

TNFEN11 : Enable noise filter of TI11
bits : 1 - 2 (2 bit)

TNFEN12 : Enable noise filter of TI12
bits : 2 - 4 (3 bit)

TNFEN13 : Enable noise filter of TI13
bits : 3 - 6 (4 bit)

TNFEN14 : Enable noise filter of TI14
bits : 4 - 8 (5 bit)

TNFEN15 : Enable noise filter of TI15
bits : 5 - 10 (6 bit)

TNFEN16 : Enable noise filter of TI16
bits : 6 - 12 (7 bit)

TNFEN17 : Enable noise filter of TI17
bits : 7 - 14 (8 bit)


ISC

Input switch control register
address_offset : 0x3 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISC ISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISC0 ISC1 SSIE00

ISC0 : The input selection of INTP0
bits : 0 - 0 (1 bit)

Enumeration:

0 : INTP0

Select INTP0 as the input of INTP0

1 : RXD0

Select RXD0 as the input of INTP0

End of enumeration elements list.

ISC1 : The input selection of TI03
bits : 1 - 2 (2 bit)

Enumeration:

0 : TI03

Select TI03 as the input of TI03

1 : RXD0

Select RXD0 as the input of TI03

End of enumeration elements list.

SSIE00 : The slave select input (SS00) of SPI00 is valid
bits : 7 - 14 (8 bit)

Enumeration:

0 : INVALID

The slave select input (SS00) pin is invalid

1 : VALID

The slave select input (SS00) pin is valid

End of enumeration elements list.


TIOS0

Timer I/O select register 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIOS0 TIOS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIOS1

Timer I/O select register 1
address_offset : 0x5 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIOS1 TIOS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTCCL

Real-time clock select register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTCCL RTCCL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.