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QSPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

SFMSMD

SFMCOM

SFMCMD

SFMCST

SFMSIC

SFMSAC

SFMSDC

SFMSPC

SFMPMD

SFMSSC

SFMSKC

SFMCNT1

SFMSST


SFMSMD

Transfer Mode Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSMD SFMSMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMRM SFMSE SFMPFE SFMPAE SFMMD3 SFMOEX SFMOHW SFMOSW SFMCCE

SFMRM : Serial interface read mode select
bits : 0 - 2 (3 bit)

SFMSE : QSSL extension function select after SPI bus access
bits : 4 - 9 (6 bit)

SFMPFE : Prefetch function select
bits : 6 - 12 (7 bit)

SFMPAE : Function select for stopping prefetch at locations other than on byte boundaries
bits : 7 - 14 (8 bit)

SFMMD3 : SPI mode select. An initial value is determined by input to CFGMD3
bits : 8 - 16 (9 bit)

SFMOEX : Extension select for the I/O buffer output enable signal for the serial interface
bits : 9 - 18 (10 bit)

SFMOHW : Hold time adjustment for serial transmission
bits : 10 - 20 (11 bit)

SFMOSW : Setup time adjustment for serial transmission
bits : 11 - 22 (12 bit)

SFMCCE : Read instruction code select
bits : 15 - 30 (16 bit)


SFMCOM

Communication Port Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMCOM SFMCOM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMD

SFMD : Port for direct communication with the SPI bus
bits : 0 - 7 (8 bit)


SFMCMD

Communication Mode Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMCMD SFMCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCOM

DCOM : Mode select for communication with the SPI bus
bits : 0 - 0 (1 bit)


SFMCST

Communication Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMCST SFMCST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMBSY EROMR

COMBSY : SPI bus cycle completion state in direct communication
bits : 0 - 0 (1 bit)
access : read-only

EROMR : ROM access detection status in direct communication mode
bits : 8 - 16 (9 bit)


SFMSIC

Instruction Code Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSIC SFMSIC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMCIC

SFMCIC : Serial flash instruction code to substitute
bits : 0 - 7 (8 bit)


SFMSAC

Address Mode Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSAC SFMSAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMAS SFM4BC

SFMAS : Number of address bytes select for the serial interface
bits : 0 - 0 (1 bit)

SFM4BC : Default instruction code select
bits : 4 - 8 (5 bit)


SFMSDC

Dummy Cycle Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSDC SFMSDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMDN SFMXST SFMXEN SFMXD

SFMDN : Number of dummy cycles select for Fast Read instructions
bits : 0 - 3 (4 bit)

SFMXST : XIP mode status
bits : 6 - 12 (7 bit)
access : read-only

SFMXEN : XIP mode permission
bits : 7 - 14 (8 bit)

SFMXD : Mode data for serial flash (control XIP mode)
bits : 8 - 23 (16 bit)


SFMSPC

SPI Protocol Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSPC SFMSPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMSPI SFMSDE

SFMSPI : SPI protocol select
bits : 0 - 1 (2 bit)

SFMSDE : Minimum time select for input output switch
bits : 4 - 8 (5 bit)


SFMPMD

Port Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMPMD SFMPMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMWPL

SFMWPL : WP pin specification
bits : 2 - 4 (3 bit)


SFMSSC

Chip Selection Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSSC SFMSSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMSW SFMSHD SFMSLD

SFMSW : Minimum high-level width select for QSSL signal
bits : 0 - 3 (4 bit)

SFMSHD : QSSL signal release timing select
bits : 4 - 8 (5 bit)

SFMSLD : QSSL signal output timing select
bits : 5 - 10 (6 bit)


SFMSKC

Clock Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMSKC SFMSKC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFMDV SFMDTY

SFMDV : Serial interface reference cycle select
bits : 0 - 4 (5 bit)

SFMDTY : Duty ratio correction function select for the QSPCLK signal
bits : 5 - 10 (6 bit)


SFMCNT1

External QSPI Address Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SFMCNT1 SFMCNT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPI_EXT

QSPI_EXT : Bank switching address
bits : 26 - 57 (32 bit)


SFMSST

Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SFMSST SFMSST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PFCNT PFFUL PFOFF

PFCNT : Number of bytes of prefetched data
bits : 0 - 4 (5 bit)

PFFUL : Prefetch buffer state
bits : 6 - 12 (7 bit)

PFOFF : Prefetch function operation state
bits : 7 - 14 (8 bit)



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