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SSI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

SSICR

SSIFCR

SSIFSR

SSIFTDR

SSIFRDR

SSITDMR

SSISCR

SSISR


SSICR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSICR SSICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REN TEN MUEN CKDV DEL PDTA SDTA SPDP LRCKP BCKP MST SWL DWL IIEN ROIEN RUIEN TOIEN TUIEN CKS

REN : Reception Enable
bits : 0 - 0 (1 bit)

TEN : Transmission Enable
bits : 1 - 2 (2 bit)

MUEN : Mute Enable
bits : 3 - 6 (4 bit)

CKDV : Select Bit Clock Division Ratio
bits : 4 - 11 (8 bit)

DEL : Select Serial Data Delay
bits : 8 - 16 (9 bit)

PDTA : Select Placement Data Alignment
bits : 9 - 18 (10 bit)

SDTA : Select Serial Data Alignment
bits : 10 - 20 (11 bit)

SPDP : Select Serial Padding Polarity
bits : 11 - 22 (12 bit)

LRCKP : Select the Initial Value and Polarity of LR Clock/Frame Synchronization Signal
bits : 12 - 24 (13 bit)

BCKP : Select Bit Clock Polarity
bits : 13 - 26 (14 bit)

MST : Master Enable
bits : 14 - 28 (15 bit)

SWL : Select System Word Length
bits : 16 - 34 (19 bit)

DWL : Select Data Word Length
bits : 19 - 40 (22 bit)

IIEN : Idle Mode Interrupt Output Enable
bits : 25 - 50 (26 bit)

ROIEN : Receive Overflow Interrupt Output Enable
bits : 26 - 52 (27 bit)

RUIEN : Receive Underflow Interrupt Output Enable
bits : 27 - 54 (28 bit)

TOIEN : Transmit Overflow Interrupt Output Enable
bits : 28 - 56 (29 bit)

TUIEN : Transmit Underflow Interrupt Output Enable
bits : 29 - 58 (30 bit)

CKS : Select an Audio Clock for Master Mode Communication
bits : 30 - 60 (31 bit)


SSIFCR

FIFO Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSIFCR SSIFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFRST TFRST RIE TIE BSW SSIRST AUCKE

RFRST : Receive FIFO Data Register Reset
bits : 0 - 0 (1 bit)

TFRST : Transmit FIFO Data Register Reset
bits : 1 - 2 (2 bit)

RIE : Receive Data Full Interrupt Output Enable
bits : 3 - 6 (4 bit)

TIE : Transmit Data Empty Interrupt Output Enable
bits : 4 - 8 (5 bit)

BSW : Byte Swap Enable
bits : 11 - 22 (12 bit)

SSIRST : Software Reset
bits : 16 - 32 (17 bit)

AUCKE : AUDIO_MCK Enable in Master Mode Communication
bits : 31 - 62 (32 bit)


SSIFSR

FIFO Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSIFSR SSIFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDF RDC TDE TDC

RDF : Receive Data Full Flag
bits : 0 - 0 (1 bit)

RDC : Number of Receive FIFO Data Indication Flag
bits : 8 - 19 (12 bit)

TDE : Transmit Data Empty Flag
bits : 15 - 30 (16 bit)

TDC : Number of Transmit FIFO Data Indication Flag
bits : 24 - 51 (28 bit)


SSIFTDR

Transmit FIFO Data Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSIFTDR SSIFTDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SSIFRDR

Receive FIFO Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSIFRDR SSIFRDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SSITDMR

TDM Mode Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSITDMR SSITDMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OMOD LRCONT BCKASTP

OMOD : Audio Format Select
bits : 0 - 1 (2 bit)

LRCONT : Enable LRCK/FS Continuation
bits : 8 - 16 (9 bit)
access : read-only

BCKASTP : Enable Stopping BCK Output When SSIE is in Idle Status
bits : 9 - 18 (10 bit)


SSISCR

Status Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSISCR SSISCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDFS TDES

RDFS : RDF Setting Condition Select
bits : 0 - 2 (3 bit)

TDES : TDE Setting Condition Select
bits : 8 - 18 (11 bit)


SSISR

Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSISR SSISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IIRQ ROIRQ RUIRQ TOIRQ TUIRQ

IIRQ : Idle Mode Status Flag
bits : 25 - 50 (26 bit)

ROIRQ : Receive Overflow Error Status Flag
bits : 26 - 52 (27 bit)

RUIRQ : Receive Underflow Error Status Flag
bits : 27 - 54 (28 bit)

TOIRQ : Transmit Overflow Error Status Flag
bits : 28 - 56 (29 bit)

TUIRQ : Transmit Underflow Error Status Flag
bits : 29 - 58 (30 bit)



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