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LCDB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

LBCTL

LBCYC

LBDATA

LBDATAL

LBDATAR

LBDATARL

LBWST


LBCTL

LCD Bus Interface mode register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBCTL LBCTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BYF TPF TCIS LBC IMD EL

BYF : Data register busy flag
bits : 0 - 0 (1 bit)

TPF : Flag of transfer in progress on external bus interface
bits : 1 - 2 (2 bit)

TCIS : INTLCDB (DMA trigger) generation control bit
bits : 3 - 6 (4 bit)

LBC : Internal clock (SPCLK) selection
bits : 4 - 9 (6 bit)

IMD : Mode of external bus interface access selection
bits : 6 - 12 (7 bit)

EL : Control the level of signal E in mod68 mode
bits : 7 - 14 (8 bit)


LBCYC

LCB Bus Interface cycle control register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBCYC LBCYC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

LBDATA

LCD Bus Interface data register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBDATA LBDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LBDATAL

SPI data register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : LBDATA
reset_Mask : 0x0

LBDATAL LBDATAL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

LBDATAR

LCD Bus Interface read data register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBDATAR LBDATAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LBDATARL

LCD Bus Interface read data register
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : LBDATAR
reset_Mask : 0x0

LBDATARL LBDATARL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

LBWST

LCB Bus Interface wait control register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBWST LBWST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0


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