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USBF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x500 byte (0x0)
mem_usage : registers
protection :

Registers

SYSCFG

CFIFO

CFIFOL

D0FIFO

D0FIFOL

D1FIFO

D1FIFOL

CFIFOSEL

CFIFOCTR

D0FIFOSEL

D0FIFOCTR

D1FIFOSEL

D1FIFOCTR

INTENB0

INTENB1

BRDYENB

NRDYENB

BEMPENB

SOFCFG

SYSSTS0

INTSTS0

INTSTS1

BRDYSTS

NRDYSTS

BEMPSTS

FRMNUM

USBREQ

USBVAL

USBINDX

USBLENG

DCPCFG

DCPMAXP

DCPCTR

PIPESEL

PIPECFG

PIPEMAXP

PIPEPERI

PIPE1CTR

PIPE2CTR

PIPE3CTR

PIPE4CTR

PIPE5CTR

PIPE6CTR

PIPE7CTR

PIPE8CTR

DVSTCTR0

PIPE9CTR

PIPE1TRE

PIPE1TRN

PIPE2TRE

PIPE2TRN

PIPE3TRE

PIPE3TRN

PIPE4TRE

PIPE4TRN

PIPE5TRE

PIPE5TRN

USBBCCTRL

USBMC

DEVADDn0

DEVADDn1

DEVADDn2

DEVADDn3

DEVADDn4

DEVADDn5


SYSCFG

System Configuration Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCFG SYSCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBE DMRPU DPRPU DRPD DCFM CNEN SCKE

USBE : USBFS Operation Enable
bits : 0 - 0 (1 bit)

DMRPU : D- Line Resistor Control
bits : 3 - 6 (4 bit)

DPRPU : D+ Line Resistor Control
bits : 4 - 8 (5 bit)

DRPD : D+/D- Line Resistor Control
bits : 5 - 10 (6 bit)

DCFM : Controller Function Select
bits : 6 - 12 (7 bit)

CNEN : CNEN Single-Ended Receiver Enable
bits : 8 - 16 (9 bit)

SCKE : USB Clock Enable
bits : 10 - 20 (11 bit)


CFIFO

CFIFO Port Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFIFO CFIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CFIFOL

CFIFO Port Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : CFIFO
reset_Mask : 0x0

CFIFOL CFIFOL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

D0FIFO

D0FIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D0FIFO D0FIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D0FIFOL

D0FIFO Port Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D0FIFO
reset_Mask : 0x0

D0FIFOL D0FIFOL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

D1FIFO

D1FIFO Port Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D1FIFO D1FIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D1FIFOL

D1FIFO Port Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : D1FIFO
reset_Mask : 0x0

D1FIFOL D1FIFOL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

CFIFOSEL

CFIFO Port Select Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFIFOSEL CFIFOSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURPIPE ISEL BIGEND MBW REW RCNT

CURPIPE : CFIFO Port Access Pipe Specification
bits : 0 - 3 (4 bit)

ISEL : CFIFO Port Access Direction When DCP is Selected
bits : 5 - 10 (6 bit)

BIGEND : CFIFO Port Endian Control
bits : 8 - 16 (9 bit)

MBW : CFIFO Port Access Bit Width
bits : 10 - 20 (11 bit)

REW : USB_EXICEN Output Pin Contro
bits : 14 - 28 (15 bit)

RCNT : Read Count Mode
bits : 15 - 30 (16 bit)


CFIFOCTR

CFIFO Port Control Register
address_offset : 0x22 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFIFOCTR CFIFOCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTLN FRDY BCLR BVAL

DTLN : Receive Data Length
bits : 0 - 7 (8 bit)

FRDY : FIFO Port Ready
bits : 13 - 26 (14 bit)

BCLR : CPU Buffer Clear
bits : 14 - 28 (15 bit)

BVAL : Buffer Memory Valid Flag
bits : 15 - 30 (16 bit)


D0FIFOSEL

D0FIFO Port Select Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D0FIFOSEL D0FIFOSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURPIPE BIGEND MBW DREQE DCLRM REW RCNT

CURPIPE : FIFO Port Access Pipe Specification
bits : 0 - 3 (4 bit)

BIGEND : FIFO Port Endian Control
bits : 8 - 16 (9 bit)

MBW : FIFO Port Access Bit Width
bits : 10 - 20 (11 bit)

DREQE : DMA/DTC Transfer Request Enable
bits : 12 - 24 (13 bit)

DCLRM : Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read
bits : 13 - 26 (14 bit)

REW : USB_EXICEN Output Pin Contro
bits : 14 - 28 (15 bit)

RCNT : Read Count Mode
bits : 15 - 30 (16 bit)


D0FIFOCTR

D1FIFO Port Control Register
address_offset : 0x2A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D0FIFOCTR D0FIFOCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D1FIFOSEL

D1FIFO Port Select Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D1FIFOSEL D1FIFOSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D1FIFOCTR

D1FIFO Port Control Register
address_offset : 0x2E Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D1FIFOCTR D1FIFOCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INTENB0

Interrupt Enable Register 0
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENB0 INTENB0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRDYE NRDYE BEMPE CTRE DVSE SOFE RSME VBSE

BRDYE : Buffer Ready Interrupt Enable
bits : 8 - 16 (9 bit)

NRDYE : Buffer Not Ready Response Interrupt Enable
bits : 9 - 18 (10 bit)

BEMPE : Buffer Empty Interrupt Enable
bits : 10 - 20 (11 bit)

CTRE : Control Transfer Stage Transition Interrupt Enable
bits : 11 - 22 (12 bit)

DVSE : Device State Transition Interrupt Enable
bits : 12 - 24 (13 bit)

SOFE : Frame Number Update Interrupt Enable
bits : 13 - 26 (14 bit)

RSME : Resume Interrupt Enable
bits : 14 - 28 (15 bit)

VBSE : VBUS Interrupt Enable
bits : 15 - 30 (16 bit)


INTENB1

Interrupt Enable Register 1
address_offset : 0x32 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENB1 INTENB1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDDETINTE0 SACKE SIGNE EOFERRE ATTCHE DTCHE BCHGE OVRCRE

PDDETINTE0 : PDDETINT0 Detection Interrupt Enable
bits : 0 - 0 (1 bit)

SACKE : Setup Transaction Normal Response Interrupt Enable
bits : 4 - 8 (5 bit)

SIGNE : Setup Transaction Error Interrupt Enable
bits : 5 - 10 (6 bit)

EOFERRE : Setup Transaction Error Interrupt Enable
bits : 6 - 12 (7 bit)

ATTCHE : Connection Detection Interrupt Enable
bits : 11 - 22 (12 bit)

DTCHE : Disconnection Detection Interrupt Enable
bits : 12 - 24 (13 bit)

BCHGE : USB Bus Change Interrupt Enable
bits : 14 - 28 (15 bit)

OVRCRE : Overcurrent Input Change Interrupt Enable
bits : 15 - 30 (16 bit)


BRDYENB

BRDY Interrupt Enable Register
address_offset : 0x36 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRDYENB BRDYENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0BRDYE PIPE1BRDYE PIPE2BRDYE PIPE3BRDYE PIPE4BRDYE PIPE5BRDYE PIPE6BRDYE PIPE7BRDYE PIPE8BRDYE PIPE9BRDYE

PIPE0BRDYE : BRDY Interrupt Enable for Pipe 0
bits : 0 - 0 (1 bit)

PIPE1BRDYE : BRDY Interrupt Enable for Pipe 1
bits : 1 - 2 (2 bit)

PIPE2BRDYE : BRDY Interrupt Enable for Pipe 2
bits : 2 - 4 (3 bit)

PIPE3BRDYE : BRDY Interrupt Enable for Pipe 3
bits : 3 - 6 (4 bit)

PIPE4BRDYE : BRDY Interrupt Enable for Pipe 4
bits : 4 - 8 (5 bit)

PIPE5BRDYE : BRDY Interrupt Enable for Pipe 5
bits : 5 - 10 (6 bit)

PIPE6BRDYE : BRDY Interrupt Enable for Pipe 6
bits : 6 - 12 (7 bit)

PIPE7BRDYE : BRDY Interrupt Enable for Pipe 7
bits : 7 - 14 (8 bit)

PIPE8BRDYE : BRDY Interrupt Enable for Pipe 8
bits : 8 - 16 (9 bit)

PIPE9BRDYE : BRDY Interrupt Enable for Pipe 9
bits : 9 - 18 (10 bit)


NRDYENB

NRDY Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NRDYENB NRDYENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0NRDYE PIPE1NRDYE PIPE2NRDYE PIPE3NRDYE PIPE4NRDYE PIPE5NRDYE PIPE6NRDYE PIPE7NRDYE PIPE8NRDYE PIPE9NRDYE

PIPE0NRDYE : NRDY Interrupt Enable for Pipe 0
bits : 0 - 0 (1 bit)

PIPE1NRDYE : NRDY Interrupt Enable for Pipe 1
bits : 1 - 2 (2 bit)

PIPE2NRDYE : NRDY Interrupt Enable for Pipe 2
bits : 2 - 4 (3 bit)

PIPE3NRDYE : NRDY Interrupt Enable for Pipe 3
bits : 3 - 6 (4 bit)

PIPE4NRDYE : NRDY Interrupt Enable for Pipe 4
bits : 4 - 8 (5 bit)

PIPE5NRDYE : NRDY Interrupt Enable for Pipe 5
bits : 5 - 10 (6 bit)

PIPE6NRDYE : NRDY Interrupt Enable for Pipe 6
bits : 6 - 12 (7 bit)

PIPE7NRDYE : NRDY Interrupt Enable for Pipe 7
bits : 7 - 14 (8 bit)

PIPE8NRDYE : NRDY Interrupt Enable for Pipe 8
bits : 8 - 16 (9 bit)

PIPE9NRDYE : NRDY Interrupt Enable for Pipe 9
bits : 9 - 18 (10 bit)


BEMPENB

BEMP Interrupt Enable Register
address_offset : 0x3A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BEMPENB BEMPENB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0BEMPE PIPE1BEMPE PIPE2BEMPE PIPE3BEMPE PIPE4BEMPE PIPE5BEMPE PIPE6BEMPE PIPE7BEMPE PIPE8BEMPE PIPE9BEMPE

PIPE0BEMPE : BEMP Interrupt Enable for Pipe 0
bits : 0 - 0 (1 bit)

PIPE1BEMPE : BEMP Interrupt Enable for Pipe 1
bits : 1 - 2 (2 bit)

PIPE2BEMPE : BEMP Interrupt Enable for Pipe 2
bits : 2 - 4 (3 bit)

PIPE3BEMPE : BEMP Interrupt Enable for Pipe 3
bits : 3 - 6 (4 bit)

PIPE4BEMPE : BEMP Interrupt Enable for Pipe 4
bits : 4 - 8 (5 bit)

PIPE5BEMPE : BEMP Interrupt Enable for Pipe 5
bits : 5 - 10 (6 bit)

PIPE6BEMPE : BEMP Interrupt Enable for Pipe 6
bits : 6 - 12 (7 bit)

PIPE7BEMPE : BEMP Interrupt Enable for Pipe 7
bits : 7 - 14 (8 bit)

PIPE8BEMPE : BEMP Interrupt Enable for Pipe 8
bits : 8 - 16 (9 bit)

PIPE9BEMPE : BEMP Interrupt Enable for Pipe 9
bits : 9 - 18 (10 bit)


SOFCFG

SOF Output Configuration Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOFCFG SOFCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EDGESTS BRDYM TRNENSEL

EDGESTS : Edge Interrupt Output Status Monitor
bits : 4 - 8 (5 bit)

BRDYM : BRDY Interrupt Status Clear Timing
bits : 6 - 12 (7 bit)

TRNENSEL : Transaction-Enabled Time Select
bits : 8 - 16 (9 bit)


SYSSTS0

System Configuration Status Register 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSSTS0 SYSSTS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNST DMRPU HTACT OVCMON

LNST : USB Data Line Status Monitor
bits : 0 - 1 (2 bit)

DMRPU : External ID0 Input Pin Monitor
bits : 2 - 4 (3 bit)

HTACT : USB Host Sequencer Status Monitor
bits : 6 - 12 (7 bit)

OVCMON : External USB_OVRCURA/USB_OVRCURB Input Pin Monitor
bits : 14 - 29 (16 bit)


INTSTS0

Interrupt Status Register 0
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTS0 INTSTS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTSQ VALID DVSQ VBSTS BRDY NRDY BEMP CTRT DVST SOFR RESM VBINT

CTSQ : Control Transfer Stage
bits : 0 - 2 (3 bit)

VALID : USB Request Reception
bits : 3 - 6 (4 bit)

DVSQ : Device State
bits : 4 - 10 (7 bit)

VBSTS : VBUS Input Status
bits : 7 - 14 (8 bit)

BRDY : Buffer Ready Interrupt Status
bits : 8 - 16 (9 bit)

NRDY : Buffer Not Ready Interrupt Status
bits : 9 - 18 (10 bit)

BEMP : Buffer Empty Interrupt Status
bits : 10 - 20 (11 bit)

CTRT : Control Transfer Stage Transition Interrupt Status
bits : 11 - 22 (12 bit)

DVST : Device State Transition Interrupt Status
bits : 12 - 24 (13 bit)

SOFR : Frame Number Update Interrupt Status
bits : 13 - 26 (14 bit)

RESM : Resume Interrupt Status
bits : 14 - 28 (15 bit)

VBINT : VBUS Interrupt Status
bits : 15 - 30 (16 bit)


INTSTS1

Interrupt Status Register 1
address_offset : 0x42 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSTS1 INTSTS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDDETINT0 SACK SIGN EOFERR ATTCH DTCH BCHG OVRCR

PDDETINT0 : PDDETINT0 Detection Interrupt Status
bits : 0 - 0 (1 bit)

SACK : Setup Transaction Normal Response Interrupt Status
bits : 4 - 8 (5 bit)

SIGN : Setup Transaction Error Interrupt Status
bits : 5 - 10 (6 bit)

EOFERR : Setup Transaction Error Interrupt Status
bits : 6 - 12 (7 bit)

ATTCH : Connection Detection Interrupt Status
bits : 11 - 22 (12 bit)

DTCH : Disconnection Detection Interrupt Status
bits : 12 - 24 (13 bit)

BCHG : USB Bus Change Interrupt Status
bits : 14 - 28 (15 bit)

OVRCR : Overcurrent Input Change Interrupt Status
bits : 15 - 30 (16 bit)


BRDYSTS

BRDY Interrupt Status Register
address_offset : 0x46 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRDYSTS BRDYSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0BRDY PIPE1BRDY PIPE2BRDY PIPE3BRDY PIPE4BRDY PIPE5BRDY PIPE6BRDY PIPE7BRDY PIPE8BRDY PIPE9BRDY

PIPE0BRDY : BRDY Interrupt Status for Pipe 0
bits : 0 - 0 (1 bit)

PIPE1BRDY : BRDY Interrupt Status for Pipe 1
bits : 1 - 2 (2 bit)

PIPE2BRDY : BRDY Interrupt Status for Pipe 2
bits : 2 - 4 (3 bit)

PIPE3BRDY : BRDY Interrupt Status for Pipe 3
bits : 3 - 6 (4 bit)

PIPE4BRDY : BRDY Interrupt Status for Pipe 4
bits : 4 - 8 (5 bit)

PIPE5BRDY : BRDY Interrupt Status for Pipe 5
bits : 5 - 10 (6 bit)

PIPE6BRDY : BRDY Interrupt Status for Pipe 6
bits : 6 - 12 (7 bit)

PIPE7BRDY : BRDY Interrupt Status for Pipe 7
bits : 7 - 14 (8 bit)

PIPE8BRDY : BRDY Interrupt Status for Pipe 8
bits : 8 - 16 (9 bit)

PIPE9BRDY : BRDY Interrupt Status for Pipe 9
bits : 9 - 18 (10 bit)


NRDYSTS

NRDY Interrupt Status Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NRDYSTS NRDYSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0NRDY PIPE1NRDY PIPE2NRDY PIPE3NRDY PIPE4NRDY PIPE5NRDY PIPE6NRDY PIPE7NRDY PIPE8NRDY PIPE9NRDY

PIPE0NRDY : NRDY Interrupt Status for Pipe 0
bits : 0 - 0 (1 bit)

PIPE1NRDY : NRDY Interrupt Status for Pipe 1
bits : 1 - 2 (2 bit)

PIPE2NRDY : NRDY Interrupt Status for Pipe 2
bits : 2 - 4 (3 bit)

PIPE3NRDY : NRDY Interrupt Status for Pipe 3
bits : 3 - 6 (4 bit)

PIPE4NRDY : NRDY Interrupt Status for Pipe 4
bits : 4 - 8 (5 bit)

PIPE5NRDY : NRDY Interrupt Status for Pipe 5
bits : 5 - 10 (6 bit)

PIPE6NRDY : NRDY Interrupt Status for Pipe 6
bits : 6 - 12 (7 bit)

PIPE7NRDY : NRDY Interrupt Status for Pipe 7
bits : 7 - 14 (8 bit)

PIPE8NRDY : NRDY Interrupt Status for Pipe 8
bits : 8 - 16 (9 bit)

PIPE9NRDY : NRDY Interrupt Status for Pipe 9
bits : 9 - 18 (10 bit)


BEMPSTS

BEMP Interrupt Status Register
address_offset : 0x4A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BEMPSTS BEMPSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPE0BEMP PIPE1BEMP PIPE2BEMP PIPE3BEMP PIPE4BEMP PIPE5BEMP PIPE6BEMP PIPE7BEMP PIPE8BEMP PIPE9BEMP

PIPE0BEMP : BEMP Interrupt Status for Pipe 0
bits : 0 - 0 (1 bit)

PIPE1BEMP : BEMP Interrupt Status for Pipe 1
bits : 1 - 2 (2 bit)

PIPE2BEMP : BEMP Interrupt Status for Pipe 2
bits : 2 - 4 (3 bit)

PIPE3BEMP : BEMP Interrupt Status for Pipe 3
bits : 3 - 6 (4 bit)

PIPE4BEMP : BEMP Interrupt Status for Pipe 4
bits : 4 - 8 (5 bit)

PIPE5BEMP : BEMP Interrupt Status for Pipe 5
bits : 5 - 10 (6 bit)

PIPE6BEMP : BEMP Interrupt Status for Pipe 6
bits : 6 - 12 (7 bit)

PIPE7BEMP : BEMP Interrupt Status for Pipe 7
bits : 7 - 14 (8 bit)

PIPE8BEMP : BEMP Interrupt Status for Pipe 8
bits : 8 - 16 (9 bit)

PIPE9BEMP : BEMP Interrupt Status for Pipe 9
bits : 9 - 18 (10 bit)


FRMNUM

Frame Number Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRMNUM FRMNUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRNM CRCE OVRN

FRNM : Frame Number
bits : 0 - 10 (11 bit)
access : read-only

CRCE : Receive Data Error
bits : 14 - 28 (15 bit)

OVRN : Overrun/Underrun Detection Status
bits : 15 - 30 (16 bit)


USBREQ

USB Request Type Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBREQ USBREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BMREQUESTTYPE BREQUEST

BMREQUESTTYPE : Request Type
bits : 0 - 7 (8 bit)

BREQUEST : Request
bits : 8 - 23 (16 bit)


USBVAL

USB Request Value Register
address_offset : 0x56 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBVAL USBVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

USBINDX

USB Request Index Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBINDX USBINDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

USBLENG

USB Request Length Register
address_offset : 0x5A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBLENG USBLENG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DCPCFG

DCP Configuration Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCPCFG DCPCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIR SHTNAK

DIR : Transfer Direction
bits : 4 - 8 (5 bit)

SHTNAK : Pipe Disabled at End of Transfer
bits : 7 - 14 (8 bit)


DCPMAXP

DCP Maximum Packet Size Register
address_offset : 0x5E Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCPMAXP DCPMAXP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MXPS DEVSEL

MXPS : Maximum Packet Size
bits : 0 - 6 (7 bit)

DEVSEL : Device Select
bits : 12 - 27 (16 bit)


DCPCTR

DCP Control Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCPCTR DCPCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID CCPL PBUSY SQMON SQSET SQCLR SUREQCLR SUREQ BSTS

PID : Response PID
bits : 0 - 1 (2 bit)

CCPL : Control Transfer End Enable
bits : 2 - 4 (3 bit)

PBUSY : Pipe Busy
bits : 5 - 10 (6 bit)

SQMON : Sequence Toggle Bit Monitor
bits : 6 - 12 (7 bit)

SQSET : Sequence Toggle Bit Set
bits : 7 - 14 (8 bit)

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 16 (9 bit)

SUREQCLR : SUREQ Bit Clear
bits : 11 - 22 (12 bit)

SUREQ : Setup Token Transmission
bits : 14 - 28 (15 bit)

BSTS : Buffer Status
bits : 15 - 30 (16 bit)


PIPESEL

Pipe Window Select Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPESEL PIPESEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIPESEL

PIPESEL : Pipe Window Select
bits : 0 - 3 (4 bit)


PIPECFG

Pipe Configuration Register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPECFG PIPECFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPNUM DIR SHTNAK DBLB BFRE TYPE

EPNUM : Endpoint Number
bits : 0 - 3 (4 bit)

DIR : Transfer Direction
bits : 4 - 8 (5 bit)

SHTNAK : Pipe Disabled at End of Transfer
bits : 7 - 14 (8 bit)

DBLB : Double Buffer Mode
bits : 9 - 18 (10 bit)

BFRE : BRDY Interrupt Operation Specification
bits : 10 - 20 (11 bit)

TYPE : Transfer Type
bits : 14 - 29 (16 bit)


PIPEMAXP

Pipe Maximum Packet Size Register
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPEMAXP PIPEMAXP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MXPS DEVSEL

MXPS : Maximum Packet Size
bits : 0 - 8 (9 bit)

DEVSEL : Device Select
bits : 12 - 27 (16 bit)


PIPEPERI

Pipe Cycle Control Register
address_offset : 0x6E Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPEPERI PIPEPERI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IITV IFIS

IITV : Interval Error Detection Interval
bits : 0 - 2 (3 bit)

IFIS : Isochronous IN Buffer Flush
bits : 12 - 24 (13 bit)


PIPE1CTR

PIPE1 Control Registers
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE1CTR PIPE1CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PBUSY SQMON SQSET SQCLR ACLRM ATREPM INBUFM BSTS

PID : Response PID
bits : 0 - 1 (2 bit)

PBUSY : Pipe Busy
bits : 5 - 10 (6 bit)

SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 12 (7 bit)

SQSET : Sequence Toggle Bit Set
bits : 7 - 14 (8 bit)

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 16 (9 bit)

ACLRM : Auto Buffer Clear Mode
bits : 9 - 18 (10 bit)

ATREPM : Auto Response Mode
bits : 10 - 20 (11 bit)

INBUFM : Transmit Buffer Monitor
bits : 14 - 28 (15 bit)

BSTS : Buffer Status
bits : 15 - 30 (16 bit)


PIPE2CTR

PIPE2 Control Registers
address_offset : 0x72 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE2CTR PIPE2CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE3CTR

PIPE3 Control Registers
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE3CTR PIPE3CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE4CTR

PIPE4 Control Registers
address_offset : 0x76 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE4CTR PIPE4CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE5CTR

PIPE5 Control Registers
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE5CTR PIPE5CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE6CTR

PIPE6 Control Registers
address_offset : 0x7A Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE6CTR PIPE6CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID PBUSY SQMON SQSET SQCLR ACLRM BSTS

PID : Response PID
bits : 0 - 1 (2 bit)

PBUSY : Pipe Busy
bits : 5 - 10 (6 bit)

SQMON : Sequence Toggle Bit Confirmation
bits : 6 - 12 (7 bit)

SQSET : Sequence Toggle Bit Set
bits : 7 - 14 (8 bit)

SQCLR : Sequence Toggle Bit Clear
bits : 8 - 16 (9 bit)

ACLRM : Auto Buffer Clear Mode
bits : 9 - 18 (10 bit)

BSTS : Buffer Status
bits : 15 - 30 (16 bit)


PIPE7CTR

PIPE7 Control Registers
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE7CTR PIPE7CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE8CTR

PIPE8 Control Registers
address_offset : 0x7E Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE8CTR PIPE8CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DVSTCTR0

Device State Control Register 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVSTCTR0 DVSTCTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RHST UACT RESUME USBRST RWUPE WKUP VBUSEN EXICEN HNPBTOA

RHST : USB Bus Reset Status
bits : 0 - 2 (3 bit)

UACT : USB Bus Enable
bits : 4 - 8 (5 bit)

RESUME : Resume Output
bits : 5 - 10 (6 bit)

USBRST : USB Bus Reset Output
bits : 6 - 12 (7 bit)

RWUPE : Wakeup Detection Enable
bits : 7 - 14 (8 bit)

WKUP : Wakeup Output
bits : 8 - 16 (9 bit)

VBUSEN : USB_VBUSEN Output Pin Control
bits : 9 - 18 (10 bit)

EXICEN : USB_EXICEN Output Pin Contro
bits : 10 - 20 (11 bit)

HNPBTOA : Host Negotiation Protocol (HNP) Control
bits : 11 - 22 (12 bit)


PIPE9CTR

PIPE9 Control Registers
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE9CTR PIPE9CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE1TRE

PIPE%s Transaction Counter Enable Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE1TRE PIPE1TRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCLR TRENB

TRCLR : Transaction Counter Clear
bits : 8 - 16 (9 bit)

TRENB : Transaction Counter Enable
bits : 9 - 18 (10 bit)


PIPE1TRN

PIPE%s Transaction Counter Register
address_offset : 0x92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE1TRN PIPE1TRN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE2TRE

PIPE%s Transaction Counter Enable Register
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE2TRE PIPE2TRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCLR TRENB

TRCLR : Transaction Counter Clear
bits : 8 - 16 (9 bit)

TRENB : Transaction Counter Enable
bits : 9 - 18 (10 bit)


PIPE2TRN

PIPE%s Transaction Counter Register
address_offset : 0x96 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE2TRN PIPE2TRN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE3TRE

PIPE%s Transaction Counter Enable Register
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE3TRE PIPE3TRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCLR TRENB

TRCLR : Transaction Counter Clear
bits : 8 - 16 (9 bit)

TRENB : Transaction Counter Enable
bits : 9 - 18 (10 bit)


PIPE3TRN

PIPE%s Transaction Counter Register
address_offset : 0x9A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE3TRN PIPE3TRN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE4TRE

PIPE%s Transaction Counter Enable Register
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE4TRE PIPE4TRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCLR TRENB

TRCLR : Transaction Counter Clear
bits : 8 - 16 (9 bit)

TRENB : Transaction Counter Enable
bits : 9 - 18 (10 bit)


PIPE4TRN

PIPE%s Transaction Counter Register
address_offset : 0x9E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE4TRN PIPE4TRN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE5TRE

PIPE%s Transaction Counter Enable Register
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE5TRE PIPE5TRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCLR TRENB

TRCLR : Transaction Counter Clear
bits : 8 - 16 (9 bit)

TRENB : Transaction Counter Enable
bits : 9 - 18 (10 bit)


PIPE5TRN

PIPE%s Transaction Counter Register
address_offset : 0xA2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIPE5TRN PIPE5TRN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

USBBCCTRL

BC Control Register 0
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBBCCTRL USBBCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPDME0 IDPSRCE0 IDMSINKE0 VDPSRCE0 IDPSINKE0 VDMSRCE0 BATCHGE0 CHGDETSTS0 PDDETSTS0

RPDME0 : D- Pin Pull-Down Control
bits : 0 - 0 (1 bit)

IDPSRCE0 : D+ Pin IDPSRC Output Control
bits : 1 - 2 (2 bit)

IDMSINKE0 : D- Pin 0.6 V Input Detection (Comparator and Sink) Control
bits : 2 - 4 (3 bit)

VDPSRCE0 : D+ Pin VDPSRC (0.6 V) Output Contro
bits : 3 - 6 (4 bit)

IDPSINKE0 : D+ Pin 0.6 V Input Detection (Comparator and Sink) Control
bits : 4 - 8 (5 bit)

VDMSRCE0 : D- Pin VDMSRC (0.6 V) Output Contro
bits : 5 - 10 (6 bit)

BATCHGE0 : BC (Battery Charger) Function General Enable Control
bits : 7 - 14 (8 bit)

CHGDETSTS0 : D- Pin 0.6 V Input Detection Status
bits : 8 - 16 (9 bit)

PDDETSTS0 : D+ Pin 0.6 V Input Detection Status
bits : 9 - 18 (10 bit)


USBMC

USB Module Control Register
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBMC USBMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDDUSBE VDCEN

VDDUSBE : USB Reference Power Supply Circuit On/Off Control
bits : 0 - 0 (1 bit)

VDCEN : USB Regulator On/Off Control
bits : 7 - 14 (8 bit)


DEVADDn0

Device Address %s Configuration Register
address_offset : 0xD0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADDn0 DEVADDn0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 13 (8 bit)


DEVADDn1

Device Address %s Configuration Register
address_offset : 0xD2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADDn1 DEVADDn1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 13 (8 bit)


DEVADDn2

Device Address %s Configuration Register
address_offset : 0xD4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADDn2 DEVADDn2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 13 (8 bit)


DEVADDn3

Device Address %s Configuration Register
address_offset : 0xD6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADDn3 DEVADDn3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 13 (8 bit)


DEVADDn4

Device Address %s Configuration Register
address_offset : 0xD8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADDn4 DEVADDn4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 13 (8 bit)


DEVADDn5

Device Address %s Configuration Register
address_offset : 0xDA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVADDn5 DEVADDn5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBSPD

USBSPD : Transfer Speed of Communication Target Device
bits : 6 - 13 (8 bit)



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