\n

DBG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

DBGSTR

DBGSTOPCR


DBGSTR

Debug status register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DBGSTR DBGSTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDBGPWRUPREQ CDBGPWRUPACK

CDBGPWRUPREQ : DBG Power Up Request
bits : 28 - 56 (29 bit)

CDBGPWRUPACK : DBG Power Up Acknowledgement
bits : 29 - 58 (30 bit)


DBGSTOPCR

Debug Stop Control register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGSTOPCR DBGSTOPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRZEN0 FRZEN1 RESMSK RPERMSK SWDIS

FRZEN0 : Stop Timer family macros when cpu halted
bits : 0 - 0 (1 bit)

FRZEN1 : Stop Communation family macros when cpu halted
bits : 1 - 2 (2 bit)

RESMSK : Mask internal reset in debug mode
bits : 2 - 4 (3 bit)

RPERMSK : Mask RAM parity error in debug mode
bits : 16 - 32 (17 bit)

SWDIS : SWD Disable
bits : 24 - 48 (25 bit)



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