Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection :
SSP Control Register.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSS : This field controls the number of bits transferred in each frame.
bits : 0 - 3 (4 bit)
Enumeration: ENUM
3 : 4 Bit
4-bit transfer
4 : 5 Bit
5-bit transfer
5 : 6 Bit
6-bit transfer
6 : 7 Bit
7-bit transfer
7 : 8 Bit
8-bit transfer
8 : 9 Bit
9-bit transfer
9 : 10 Bit
10-bit transfer
10 : 11 Bit
11-bit transfer
11 : 12 Bit
12-bit transfer
12 : 13 Bit
13-bit transfer
13 : 14 Bit
14-bit transfer
14 : 15 Bit
15-bit transfer
15 : 16 Bit
16-bit transfer
End of enumeration elements list.
FRF : Frame Format.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0 : SPI
SPI - compatible frame format
1 : TISS
TISS - compatible frame format
2 : Microwire
Microwire - compatible frame format
End of enumeration elements list.
CPO : SSPCLK Clock Out Polarity
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : low
SSP controller maintains the bus clock low between frames.
1 : high
SSP controller maintains the bus clock high between frames.
End of enumeration elements list.
CPH : Clock Out Phase
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0x0 : first
SSP controller captures serial data on the first transition clock edge of the frame.
0x1 : second
SSP controller captures serial data on the second transition clock edge of the frame.
End of enumeration elements list.
SOD : Slave Output Disable
bits : 8 - 16 (9 bit)
Enumeration: ENUM
0 : Disable
SSP can drive the MISO output in slave mode.
1 : Enable
SSP must not drive the MISO output in slave mode.
End of enumeration elements list.
MS : Master/Slave Mode
bits : 9 - 18 (10 bit)
Enumeration: ENUM
0 : Disable
The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.
1 : Enable
The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.
End of enumeration elements list.
SSPEN : SSP Enable
bits : 10 - 20 (11 bit)
Enumeration: ENUM
0 : Disable
The SSP controller is disabled.
1 : Enable
The SSP controller will interact with other devices on the serial bus.
End of enumeration elements list.
LBM : Loop Back Mode
bits : 11 - 22 (12 bit)
Enumeration: ENUM
0 : Disable
Normal operation.
1 : Enable
Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).
End of enumeration elements list.
SSP Interrupt Mask Set and Clear Register.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RORIM : Receive Overrun Interrupt Mask.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : RORIM
Rx FIFO written to while full condition interrupt is disabled.
0 : RORIM
Rx FIFO written to while full condition interrupt is disabled.
End of enumeration elements list.
RTIM : Receive Timeout Interrupt Mask.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : RTIM
Rx FIFO not empty and no read prior to timeout period interrupt is disabled.
0 : RTIM
Rx FIFO not empty and no read prior to timeout period interrupt is disabled.
End of enumeration elements list.
RXIM : Receive FIFO Interrupt Mask.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : RXIM
Rx FIFO half full or less condition interrupt is disabled.
0 : RXIM
Rx FIFO half full or less condition interrupt is disabled.
End of enumeration elements list.
TXIM : Transmit FIFO Interrupt Mask.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : TXIM
Tx FIFO half empty or less condition interrupt is disabled.
0 : TXIM
Tx FIFO half empty or less condition interrupt is disabled.
End of enumeration elements list.
SSP Raw Interrupt Status Register.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RORRIS : This bit is 1 if another frame was completely received while the Rx FIFO was full.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : Empty
1 : full
End of enumeration elements list.
RTRIS : This bit is 1 if the Rx FIFO is not empty
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : Empty
1 : not empty
End of enumeration elements list.
RXRIS : This bit is 1 if the Rx FIFO is not empty
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : not half empty
1 : half empty
End of enumeration elements list.
TXRIS : This bit is 1 if the Tx FIFO is at least half empty.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : TX not half empty
1 : TX half empty
End of enumeration elements list.
SSP Masked Interrupt Status Register.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RORMIS : This bit is 1 if another frame was completely received while the Rx FIFO was full, and this interrupt is enabled.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : disable
1 : enable
End of enumeration elements list.
RTMIS : This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at FSSPCLK.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : disable
1 : enable
End of enumeration elements list.
RXMIS : This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : disable
1 : enable
End of enumeration elements list.
TXMIS : This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : disable
1 : enable
End of enumeration elements list.
SSP Interrupt Clear Register.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RORIC : Writing a 1 to this bit clears the rame was received when Rx FIFO was full interrupt.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
1 : 1
clear rx fifo
End of enumeration elements list.
RTIC : Writing a 1 to this bit clears the Rx FIFO was not empty and has not
bits : 1 - 2 (2 bit)
Enumeration: ENUM
1 : 1
clear rx fifo
End of enumeration elements list.
Software Control SSP CS.
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELCS : Select SSP SS0~3 active mode
bits : 0 - 1 (2 bit)
Enumeration: ENUM
2 : SELCS
SS2 line is active
2 : SELCS
SS2 line is active
2 : SELCS
SS2 line is active
2 : SELCS
SS2 line is active
End of enumeration elements list.
SWSEL : Software select mode
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : 0
Chip-Select is automatically controlled by the SPI module
1 : 1
Chip-Select is software controlled by SWCS bit
End of enumeration elements list.
SWCS : Software Chip-Select. The chip-select line selected by SELCS is controlled
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : 0
Chip-Select is low
0 : 0
Chip-Select is low
End of enumeration elements list.
SPH : As SSP slave.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : 0
Chip select signal cannot pull high after a frame transfer
1 : 1
Chip select signal must pull high after a frame transfer
End of enumeration elements list.
SSP Status Register.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFE : Transmit FIFO Empty.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : TXFIFONMP
Transmit FIFO is not empty
1 : TXFIFOEPT
Transmit FIFO is empty
End of enumeration elements list.
TNF : Transmit FIFO Not Full.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : TXFIFOFULL
Transmit FIFO is full
1 : TXFIFONFULL
Transmit FIFO is not full
End of enumeration elements list.
RNE : Receive FIFO Not Empty.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : RXFIFOEMP
Receive FIFO is empty
0 : RXFIFOEMP
Receive FIFO is empty
End of enumeration elements list.
RFF : Receive FIFO Full.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : RXFIFONFULL
Receive FIFO in not full
1 : RXFIFOFULL
Receive FIFO is full
End of enumeration elements list.
BSY : Busy flag.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : IDLE
SSP/SPI is idle
1 : nEMPT
SSP/SPI is currently transmitting and (or) receiving a frame or the transmit FIFO is not empty
End of enumeration elements list.
SSP Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA :
bits : 0 - 15 (16 bit)
SSP Clock Control Register.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
N : FSSPCLK = PCLK / ((M+1)xN) N is an even value from 2 to 254
bits : 0 - 7 (8 bit)
M :
bits : 8 - 23 (16 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.