Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection :
Receiver buffer register. Contain the next received character to be read.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RBR : The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO.
bits : 0 - 7 (8 bit)
Interrupt identification register. Identifies which interrupts are pending.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTSTATUS : Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR3-1
bits : 0 - 0 (1 bit)
Enumeration: ENUM
1 : INT STATUS
No interrupt is pending.
1 : INT STATUS
No interrupt is pending.
End of enumeration elements list.
INTID : Interrupt identification.
bits : 1 - 4 (4 bit)
Enumeration: ENUM
0 : 4 - Modem Status change.
4 - Modem Status change.
1 : 3 - TX Holding Register Empty.
3 - TX Holding Register Empty.
2 : 2a - Receive Data Available.
2a - Receive Data Available.
3 : 1 - Receive Line Status.
1 - Receive Line Status.
6 : 2b - Receive FIFO Character
2b - Receive FIFO Character
End of enumeration elements list.
INTSFC : Software Flow Control (XOFF character received) If Set (indicating that a rising edge has been detected on either the RTS/CTS Modem Control line. It is cleared by reading the Interrupt Identification Register.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
1 : INTSFC
1 : INTSFC
End of enumeration elements list.
INTHFC : Hardware Flow Control (CTS or RTS rising edge) If Set (indicating that an XOFF character has been received. It is cleared by reading the Interrupt Identification Register.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
1 : INTHFC
No interrupt is pending.
1 : INTHFC
No interrupt is pending.
End of enumeration elements list.
FIFO control register. Control UART FIFO usage and modes.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOEN : FIFO Enable
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : Disable FIFO
UART FIFOs are disabled. Must not be used in the application.
1 : Enable FIFO
Active high enable for both UART RX and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs.
End of enumeration elements list.
RXFIFORST : RX FIFO Reset
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : No impact
No impact on either of UART FIFOs.
1 : clear FIFO
Writing a logic 1 to FCR[1] will clear all bytes in UART RX FIFO, reset the pointer logic. This bit is self-clearing.
End of enumeration elements list.
TXFIFORST : TX FIFO Reset
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : no impact
No impact on either of UART FIFOs.
1 : TX FIFO Reset
Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing.
End of enumeration elements list.
TXTL : TX Trigger Level. These two bits determine how many transmit UART FIFO characters must be written before an interrupt is activated.
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0 : level 0
Trigger level 0 (1 character).
1 : level 1
Trigger level 1 (4 characters).
2 : level 2
Trigger level 2 (8 characters).
3 : level 3
Trigger level 3 (14 characters).
End of enumeration elements list.
RXTL : RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated.
bits : 6 - 13 (8 bit)
Enumeration: ENUM
0 : level 0
Trigger level 0 (1 character).
1 : level 1
Trigger level 1 (4 characters).
2 : level 2
Trigger level 2 (8 characters).
3 : level 3
Trigger level 3 (14 characters).
End of enumeration elements list.
Line status register. Contains controls for frame formatting and break generation.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLS : Word Length Select
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0 : 5-bit
5-bit character length.
1 : 6-bit
6-bit character length.
2 : 7-bit
7-bit character length.
3 : 8-bit
8-bit character length.
End of enumeration elements list.
SBS : Stop Bit Select
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : 1 Stop bit
1 stop bit.
1 : 2 Stop bit
2 stop bits (1.5 if LCR[1:0]=00).
End of enumeration elements list.
PEN : Parity Enable
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : Disable
Disable parity generation and checking.
1 : Enable
Enable parity generation and checking.
End of enumeration elements list.
PSEL : Parity Select
bits : 4 - 9 (6 bit)
Enumeration: ENUM
0 : Odd parity
Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
1 : Even parity
Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.
2 : Forced 1
Forced 1 stick parity.
3 : Forced 0
Forced 0 stick parity.
End of enumeration elements list.
BCON : Break Control
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : Disable
Disable break transmission.
1 : Enable
Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR[6] is active high.
End of enumeration elements list.
Modem control register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTS : Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : high
Drive RTS pin high.
1 : low
Drive RTS pin low.
End of enumeration elements list.
MLBM : Modem Loop back mode
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : disable
Disable modem loopback mode.
1 : enable
Enable modem loopback mode.
End of enumeration elements list.
IREN : IrDA mode enables
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : disable
IrDA mode on UART is disabled,
1 : enable
IrDA mode on UART is enabled.
End of enumeration elements list.
XOFFS : XOFF Status This read-only bit is set to 1 when an XOFF character is received and cleared when an XON character is received
bits : 7 - 14 (8 bit)
Enumeration: ENUM
1 : XOFFS
1 : XOFFS
End of enumeration elements list.
Line status register. Contain flags for transmit and receive status, including line errors.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDR : Receiver Data Ready: LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : empty
RDR is empty
1 : contains valid data
RDR contains valid data.
End of enumeration elements list.
OE : Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : inactive
Overrun error status is inactive.
1 : active
Overrun error status is active.
End of enumeration elements list.
PE : Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO.
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : inactive
Parity error status is inactive.
1 : active
Parity error status is active.
End of enumeration elements list.
FE : Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0x0 : inactive
Framing error status is inactive.
0x1 : active
Framing error status is active.
End of enumeration elements list.
BI : Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO.
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : inactive
Break interrupt status is inactive.
1 : active
Break interrupt status is active.
End of enumeration elements list.
THRE : Transmitter Holding Register Empty.THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : contains valid data
THR contains valid data.
1 : empty
THR is empty.
End of enumeration elements list.
TEMT : Transmitter Empty. TEMT is set when both THR and TSR are empty TEMT is cleared when either the TSR or the THR contain valid data.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : contains valid data
THR and/or the TSR contains valid data.
1 : empty
THR and the TSR are empty.
End of enumeration elements list.
RXFE : Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR.This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
1 : RXFE
UART RBR contains at least one UART RX error.
1 : RXFE
UART RBR contains at least one UART RX error.
End of enumeration elements list.
Modem status register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCTS : Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : No change detected
No change detected on modem input, CTS.
1 : State change detected
State change detected on modem input, CTS.
End of enumeration elements list.
CTS : Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode
bits : 4 - 8 (5 bit)
Scratch Pad Register. Eight-bit temporary storage for software.
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAD : A readable, writable byte.
bits : 0 - 7 (8 bit)
Enhanced features register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXSWFC : RX Software Flow Control
bits : 0 - 1 (2 bit)
Enumeration: ENUM
0 : No
No RX Flow Control
1 : XON1/XOFF1
Receive XON1/XOFF1 as flow control bytes
2 : XON2/XOFF2
Receive XON2/XOFF2 as flow control bytes
3 : XON1 XON2 and XOFF1 XOFF2
Receive XON1 XON2 and XOFF1 XOFF2 as flow control words
End of enumeration elements list.
TXSWFC : TX Software Flow Control
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0 : No
No TX Flow Control
1 : XON1/XOFF1
Transmit XON1/XOFF1 as flow control bytes
2 : XON2/XOFF2
Transmit XON2/XOFF2 as flow control bytes
3 : XON1 XON2 and XOFF1 XOFF2
Transmit XON1 XON2 and XOFF1 XOFF2 as flow control words
End of enumeration elements list.
MEEN : M16x50 Enhancements Enables
bits : 4 - 8 (5 bit)
Enumeration: ENUM
0 : disable
disable
1 : enable
enable
End of enumeration elements list.
AUTORTS : Enables hardware reception flow control (RTS=0, RTS pin is high)
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : disable
disable
1 : enable
enable
End of enumeration elements list.
AUTOCTS : Enables hardware transmission flow control
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : disable
disable
1 : enable
enable
End of enumeration elements list.
XON1 Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXON : hold the XON characters used in software control of transmission and reception
bits : 0 - 7 (8 bit)
XON2 Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXON : hold the XON characters used in software control of transmission and reception
bits : 0 - 7 (8 bit)
XOFF1 Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXOFF : hold the XOFF characters used in software control of transmission and reception
bits : 0 - 7 (8 bit)
XOFF2 Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXOFF : hold the XOFF characters used in software control of transmission and reception
bits : 0 - 7 (8 bit)
Transistor holding register. The next character to be transmitted is written here.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
THR : Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.
bits : 0 - 7 (8 bit)
UART Divisor Latch Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLR : Divisor Latch Register. The full divisor isused to generate a baud rate from the fractional rate divider. Baud rate = PCLK/16xDLR
bits : 0 - 15 (16 bit)
Interrupt enable register. Contains individual interrupt enable bits for the 7 potential UART interrupts.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBRIE : RX Buffer Register Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt.
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : disable
Disable the RBRIE interrupts.
1 : enable
Enable the RBRIE interrupts.
End of enumeration elements list.
THREIE : TX Holding Register Empty Interrupt Enable. Enables the THREIE interrupt for UART. The status of this interrupt can be read from LSR[5].
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : disable
Disable the THREIE interrupts.
1 : enable
Enable the THREIE interrupts.
End of enumeration elements list.
RLSIE : RX Line Status Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].
bits : 2 - 4 (3 bit)
Enumeration: ENUM
0 : disable
Disable the RX line status interrupts.
1 : enable
Enable the RX line status interrupts.
End of enumeration elements list.
MDSIE : Modem Status Interrupt Enable.
bits : 3 - 6 (4 bit)
Enumeration: ENUM
0 : disable
Disable the modem status interrupts.
1 : enable
Enable the modem status interrup
End of enumeration elements list.
XOFIE : XOFF Interrupt Enable. Enable an XOFF character is received.
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : disable
Disable the XOF interrupt.
1 : enable
Enable the XOF interrupt.
End of enumeration elements list.
RTSIE : RTS Interrupt Enable. Enable a rising edge is detected on the RTS modem control line.
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : disable
Disable the RTS interrupt.
1 : enable
Enable the RTS interrupt.
End of enumeration elements list.
CTSIE : CTS Interrupt Enable. Enable a rising edge is detected on the CTS modem control line.
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : disable
Disable the CTS interrupt.
1 : enable
Enable the CTS interrupt.
End of enumeration elements list.
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