\n
address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection :
Timer Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMROS : Selects one-shot or wrapping counter mode
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : wrapping
wrapping mode
1 : one-shot
one-shot mode
End of enumeration elements list.
TMRSZ : Selects 16/32 bit counter operation
bits : 1 - 2 (2 bit)
Enumeration: ENUM
0 : 16-bit
16-bit counter
1 : 32-bit
32-bit counter
End of enumeration elements list.
TMRPRE : Timer prescale
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0 : div 1
Clock is diveded by 1
1 : div 16
Clock is divided by 16
2 : div 256
Clock is diveded by 256
End of enumeration elements list.
TMRIE : Interrupt Enable
bits : 5 - 10 (6 bit)
Enumeration: ENUM
0 : disable
Timer interrupt disable
1 : enable
Timer interrupt enable
End of enumeration elements list.
TMRMS : Timer mode select
bits : 6 - 12 (7 bit)
Enumeration: ENUM
0 : free running mode
Timer is in free running mode
1 : periodic mode
Timer is in periodic mode
End of enumeration elements list.
TMREN : Timer Enable
bits : 7 - 14 (8 bit)
Enumeration: ENUM
0 : disable
Timer disable
1 : enable
Timer enable
End of enumeration elements list.
TimerMasked interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MIS : Enable interrupt status from the counter
bits : 0 - 0 (1 bit)
Timerclear interrupt Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ICLR : Any write to the TMRxICLR Register clears the interrupt output from the counter.
bits : 0 - 31 (32 bit)
TimerBackground Load Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BGLOAD : The TMRxBGLOAD Register is 32-bits and contains the value from which the counter is to decrement. This is the value used to reload the counter when Periodic mode is enabled, and the current count reaches zero.This register provides an alternative method of accessing the TMRxBGLOADRegister.The difference is that writes toTMRxBGLOAD do not cause the counter to immediately restart from the new value. Reading from this register returns the same value returned from TMRxLOAD.
bits : 0 - 31 (32 bit)
Timer Load Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOAD : When this register is written to directly,the current count is immediately reset to the new value at the next rising edge of TIMER CLK that is enabled by TIMER CLK enable. The value in this register is aslo overwritten if the TMRxBGLOAD Register is written to , but the current count is not immediately affected. If values are written to both the TMRxLOAD and TMRxBGLOAD Registers before an enabled rising edge on TIMER CLK, the following occurs: 1.On the next enabled TIMER CLK edge, the value written to the TMRXLOAD value replaces the current count value. 2.Then, each time the counter reaches zero, the current count value is reset to the value written to TMRxBGLOA.Reading from the TMRXLOAD Register at any time after the two writes have occurred retrieves the value written to TMRxBGLOA.That is the value that takes effect for Periodic mode after the next time the counter reaches zero.
bits : 0 - 31 (32 bit)
TimerCurrent Value Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VAL : The TMRxVAL Register gives the current value of the decrementing counter.
bits : 0 - 31 (32 bit)
TimerRaw interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RIS : Raw interrupt status from the counter
bits : 0 - 0 (1 bit)
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