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WDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection :

Registers

CON

MIS

ICLR

LOCK

LOAD

VAL

RIS


CON

Watchdog Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CON CON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTIEN WDTPRE WDTEN

WDTIEN : WDT interrupt enable bit
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : disable

disable WDT interrupt

1 : enable

enable WDT interrupt

End of enumeration elements list.

WDTPRE : WDT clock select
bits : 2 - 5 (4 bit)

Enumeration: ENUM

0 : div 1

Clock is divided by 1

1 : div 16

Clock is divided by 16

2 : div 256

Clock is divided by 256

End of enumeration elements list.

WDTEN : WDT reset enable
bits : 8 - 23 (16 bit)


MIS

Watchdog Masked Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTMIS

WDTMIS : interrupt enable bit
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : disable

Disable interrupt status from the counter

1 : enable

Enabled interrupt status from the counter

End of enumeration elements list.


ICLR

Watchdog Clear Interrupt Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICLR ICLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMLOAD

PWMLOAD : Write 0x55AA55AA clear WDT and clear over flow Flag bit.
bits : 0 - 31 (32 bit)


LOCK

Watchdog Lock Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTREN WDTKEY

WDTREN : Register write enable
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : disable

Write access to all other registers is disabled

1 : enable

Write access to all other registers is enabled

End of enumeration elements list.

WDTKEY : Enable write access to all other registers by writing 0x2AD5334C. Disable write access by writing any other value.
bits : 1 - 32 (32 bit)


LOAD

Watchdog Load Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOAD LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWMLOAD

PWMLOAD : PWM load value
bits : 0 - 31 (32 bit)


VAL

Watchdog Current Value Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VAL VAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTVAL

WDTVAL : The WDTVAL Register gives the current value of the decrementing counter.
bits : 0 - 31 (32 bit)


RIS

Watchdog Raw Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTRIS

WDTRIS : Raw interrupt status from the counter
bits : 0 - 0 (1 bit)



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