\n
address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection :
Watchdog Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTIEN : WDT interrupt enable bit
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : disable
disable WDT interrupt
1 : enable
enable WDT interrupt
End of enumeration elements list.
WDTPRE : WDT clock select
bits : 2 - 5 (4 bit)
Enumeration: ENUM
0 : div 1
Clock is divided by 1
1 : div 16
Clock is divided by 16
2 : div 256
Clock is divided by 256
End of enumeration elements list.
WDTEN : WDT reset enable
bits : 8 - 23 (16 bit)
Watchdog Masked Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDTMIS : interrupt enable bit
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : disable
Disable interrupt status from the counter
1 : enable
Enabled interrupt status from the counter
End of enumeration elements list.
Watchdog Clear Interrupt Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PWMLOAD : Write 0x55AA55AA clear WDT and clear over flow Flag bit.
bits : 0 - 31 (32 bit)
Watchdog Lock Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTREN : Register write enable
bits : 0 - 0 (1 bit)
Enumeration: ENUM
0 : disable
Write access to all other registers is disabled
1 : enable
Write access to all other registers is enabled
End of enumeration elements list.
WDTKEY : Enable write access to all other registers by writing 0x2AD5334C. Disable write access by writing any other value.
bits : 1 - 32 (32 bit)
Watchdog Load Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMLOAD : PWM load value
bits : 0 - 31 (32 bit)
Watchdog Current Value Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDTVAL : The WDTVAL Register gives the current value of the decrementing counter.
bits : 0 - 31 (32 bit)
Watchdog Raw Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDTRIS : Raw interrupt status from the counter
bits : 0 - 0 (1 bit)
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