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IIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection :

Registers

CONSET

CLK

ADR0

ADM0

XADR0

XADM0

RST

ADR1

ADM1

ADR2

ADM2

ADR3

ADM3

CONCLR

STAT

DAT


CONSET

I2C Control Set Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSET CONSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRF XADRF AA SI STO STA I2CEN I2CIE GCF

ADRF : I2C Slave Address FLAG (7-bitaddressing) (Read Only)
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : not match

I2C slave address is not match.

1 : match

I2C slave address is match with 7-bit address. This bit is clear when new data is transmit/receive.

End of enumeration elements list.

XADRF : I2C Extended Slave Address FLAG (10-bit addressing) (Read Only)
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : not match

I2C slave address is not match.

1 : match

I2C slave address is match with 10-bit address. This bit is clear when new data is transmit/receive.

End of enumeration elements list.

AA : Assert acknowledge flag. (AA can be cleared by writing 1 to the AAC bit in the I2C0CONCLR register.) (The I2C will not respond as a slave unless AA is set.) 0: A not acknowledge (HIGH level to SDA) will be returned during the acknowledge clock pulse on the SCL line, when a data byte has been received while the I2C is in the master or slave mode. 1: An acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations: 1. The add ress in the Slave Address Register has been received. 2. The General Call address has been received while the General Call bit (GC) in the ADR register is set. 3. A data byte has been received while the I2C is in the master or slave mode.
bits : 2 - 4 (3 bit)

SI : I2C interrupt flag. (SI can be cleared by writing 1 to the SIC bit in the I2C0CONCLR register.) This bit is set when the I2C state changes, and if bit I2CIE is set, the I2C interrupt is requested. However, entering state F8 does not set SI since there is nothing for an interrupt service routine to do in that case. The SI is clear by software.
bits : 3 - 6 (4 bit)

Enumeration: ENUM

0 : 0

write 0

1 : 1

write 1

End of enumeration elements list.

STO : STO flag
bits : 4 - 8 (5 bit)

Enumeration: ENUM

0 : Disable

Disable PWM0

1 : Enable

Enable PWM0

End of enumeration elements list.

STA : START flag. (STA can be cleared by writing 1 to the STAC bit in the I2C0CONCLR register.) When STA is set to one, the I2C enters master mode and will send a START condition on the bus when the bus is free. If the STA bit is set to one when the I2C is already in master mode, then a repeated START condition will be sent. If the STA bit is set to one while the I2C is being accessed in slave mode, the I2C will complete the data transfer in slave mode then enter master mode when the bus has been released.The STA bit is cleared automatically after a START condition has been sent: writing a zero to this bit has no effect.
bits : 5 - 10 (6 bit)

Enumeration: ENUM

0 : 0

write 0

1 : 1

write 1

End of enumeration elements list.

I2CEN : I2C interface enable. (I2CEN can be cleared by writing 1 to the I2CENC bit in the I2C0CONCLR register.) (The Multi-Function pin function of SDA and SCL must be set to I2C function.)
bits : 6 - 12 (7 bit)

Enumeration: ENUM

0 : Disable

Disable I2C interface.

1 : Enable

Enable I2C interface.

End of enumeration elements list.

I2CIE : Interrupt Enable
bits : 7 - 14 (8 bit)

Enumeration: ENUM

0 : Disable

Disable I2C interrupt

1 : Enable

Enable I2C interrupt

End of enumeration elements list.

GCF : I2C General Call FLAG (Read Only)
bits : 8 - 16 (9 bit)

Enumeration: ENUM

0 : not match

I2C General call address is not match.

1 : match

I2C General call address is match.This bit is clear when new data is transmit/receive.

End of enumeration elements list.


CLK

I2C Clock Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N M

N : FSAMP = PCLK / 2M
bits : 0 - 3 (4 bit)

M : FSCL = PCLK / (2Mx(N+1)x10)
bits : 4 - 10 (7 bit)


ADR0

I2C Slave Address Register 0.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADR0 ADR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GC Address

GC : General Call enable bit.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : Disable

Disable General call

1 : Enable

Enable General call

End of enumeration elements list.

Address : The I2C device address for slave mode.
bits : 1 - 8 (8 bit)


ADM0

I2C Slave Address Mask Register 0.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADM0 ADM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Mask bits
bits : 1 - 8 (8 bit)

Enumeration: ENUM

0 : low output

The received corresponding address bit doesn't care.

1 : high output

The received corresponding address bit should be exact the same as address register. The mask register has no effect on comparison to the General Call address. When an address-match interrupt occurs, the processor will have to read the data register (DAT) to determine what the received address was that actually caused the match.

End of enumeration elements list.


XADR0

I2C Extended Slave Address Register 0.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XADR0 XADR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GC Address

GC : General Call enable bit
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : disable

disable general call

1 : enable

enable general call

End of enumeration elements list.

Address : The I2C device address for slave mode.
bits : 1 - 11 (11 bit)


XADM0

I2C Extended Slave Address Mask Register 0.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XADM0 XADM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Mask bits
bits : 1 - 9 (9 bit)

Enumeration: ENUM

0 : don't care

The received corresponding address bit is don't care.

1 : care

The received corresponding address bit should be exact the same as address register. The mask register has no effect on comparison to the General Call address.When an address-match interrupt occurs, the processor will have to read the data register (DAT) to determine what the received address was that actually caused the match.

End of enumeration elements list.


RST

I2C Software Reset Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RST RST write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST

RST : I2C software reset by writes 0x07.
bits : 0 - 7 (8 bit)


ADR1

I2C Slave Address Register 1.
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADR1 ADR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GC Address

GC : General call enable bit
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : disable

disable general call

1 : enable

enable general call

End of enumeration elements list.

Address : The I2C device address for slave mode.
bits : 1 - 8 (8 bit)


ADM1

I2C Slave Address Mask Register 1.
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADM1 ADM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Mask bits
bits : 1 - 8 (8 bit)

Enumeration: ENUM

0 : low output

The received corresponding address bit doesn't care.

1 : high output

The received corresponding address bit should be exact the same as address register. The mask register has no effect on comparison to the General Call address. When an address-match interrupt occurs, the processor will have to read the data register (DAT) to determine what the received address was that actually caused the match.

End of enumeration elements list.


ADR2

I2C Slave Address Register 2.
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADR2 ADR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GC Address

GC : General call enable bit
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : disable

disable general call

1 : enable

enable general call

End of enumeration elements list.

Address : The I2C device address for slave mode.
bits : 1 - 8 (8 bit)


ADM2

I2C Slave Address MaskRegister 2.
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADM2 ADM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Mask bits
bits : 1 - 8 (8 bit)

Enumeration: ENUM

0 : low output

The received corresponding address bit doesn't care.

1 : high output

The received corresponding address bit should be exact the same as address register. The mask register has no effect on comparison to the General Call address.When an address-match interrupt occurs, the processor will have to read the data register (DAT) to determine what the received address was that actually caused the match.

End of enumeration elements list.


ADR3

I2C Slave Address Register 3.
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADR3 ADR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GC Address

GC : General call enable bit
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : disable

disable general call

1 : enable

enable general call

End of enumeration elements list.

Address : The I2C device address for slave mode.
bits : 1 - 8 (8 bit)


ADM3

I2C Slave Address Mask Register 3.
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADM3 ADM3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Mask bits
bits : 1 - 8 (8 bit)

Enumeration: ENUM

0 : low output

The received corresponding address bit doesn't care.

1 : high output

The received corresponding address bit should be exact the same as address register.The mask register has no effect on comparison to the General Call address. When an address-match interrupt occurs, the processor will have to read the data register (DAT) to determine what the received address was that actually caused the match.

End of enumeration elements list.


CONCLR

I2C Control Clear Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CONCLR CONCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AAC SIC STAC I2CENC I2CIEC

AAC : Assert acknowledge clear. Writing a 1 to this bit clears the AAC bit in the I2C0CONSET register. Writing 0 has no effect.
bits : 2 - 4 (3 bit)

SIC : I2C interrupt clear. Writing a 1 to this bit clears the SIC bit in the I2C0CONSET register. Writing 0 has no effect.
bits : 3 - 6 (4 bit)

STAC : START flag clear. Writing a 1 to this bit clears the STA bit in the I2C0CONSET register. Writing 0 has no effect.
bits : 5 - 10 (6 bit)

I2CENC : I2C interface disable. Writing a 1 to this bit clears the I2CENC bit in the I2C0CONSET register. Writing 0 has no effect.
bits : 6 - 12 (7 bit)

I2CIEC : I2C interrupt disable. Writing a 1 to this bit clears the I2CIEC bit in the I2C0CONSET register. Writing 0 has no effect.
bits : 7 - 14 (8 bit)


STAT

I2C Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Status

Status : Interrupt status code
bits : 0 - 7 (8 bit)

Enumeration: ENUM

0x00 : Bus error (Master mode only)

Bus error (Master mode only)

0x08 : START condition transmitted

START condition transmitted

0x10 : Repeated START condition transmitted

Repeated START condition transmitted

0x18 : Address + Write bit transmitted, ACK received

Address + Write bit transmitted, ACK received

0x020 : Address + Write bit transmitted, Not ACK received

Address + Write bit transmitted, Not ACK received

0x28 : Data byte transmitted in master mode, ACK received

Data byte transmitted in master mode, ACK received

0x30 : Data byte transmitted in master mode, Not ACK received

Data byte transmitted in master mode, Not ACK received

0x38 : Arbitration lost in address or data byte

Arbitration lost in address or data byte

0x40 : Address + Read bit transmitted, ACK received

Address + Read bit transmitted, ACK received

0x48 : Address + Read bit transmitted, Not ACK received

Address + Read bit transmitted, Not ACK received

0x50 : Data byte received in master mode, ACK transmitted

Data byte received in master mode, ACK transmitted

0x58 : Data byte received in master mode, Not ACK transmitted

Data byte received in master mode, Not ACK transmitted

0x60 : Slave address + Write bit received, ACK transmitted

Slave address + Write bit received, ACK transmitted

0x78 : Arbitration lost in address as master

Arbitration lost in address as master, General Call Address received, ACK transmitted

0x70 : General Call Address received, ACK transmitted

General Call Address received, ACK transmitted

0x78 : Arbitration lost in address as master

Arbitration lost in address as master, General Call Address received, ACK transmitted

0x80 : Data byte received after slave address received, ACK transmitted

Data byte received after slave address received, ACK transmitted

0x88 : Data byte received after slave address received

Data byte received after slave address received, Not ACK transmitted

0x90 : Data byte received after General Call Address received

Data byte received after General Call Address received, ACK transmitted

0x98 : Data received after General Call received, Not ACK

Data byte received after General Call Address received, Not ACK transmitted

0xA0 : STOP or repeated START condition received in slave mode

STOP or repeated START condition received in slave mode

0xA8 : Slave address + Read bit received, ACK transmitted

Slave address + Read bit received, ACK transmitted

0x78 : Arbitration lost in address as master

Arbitration lost in address as master, General Call Address received, ACK transmitted

0xB8 : Data byte transmitted in slave mode, ACK received

Data byte transmitted in slave mode, ACK received

0xC0 : Data byte transmitted in slave mode, Not ACK received

Data byte transmitted in slave mode, Not ACK received

0xC8 : Last byte transmitted in slave mode, ACK received

Last byte transmitted in slave mode, ACK received

0xD0 : Last byte transmitted in slave mode, Not ACK received

Last byte transmitted in slave mode, Not ACK received

0xD8 : Unused

Unused

0xE0 : Second Address byte transmitted, ACK received

Second Address byte transmitted, ACK received

0xE8 : Second Address byte transmitted, Not ACK received

Second Address byte transmitted, Not ACK received

0xD8 : Unused

Unused

0xF8 : No relevant status information, IFLG=0

No relevant status information, IFLG=0

End of enumeration elements list.


DAT

I2C Data Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAT DAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data

Data : This register holds data values that have been received or are to be transmitted.
bits : 0 - 7 (8 bit)



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