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SYSCON

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection :

Registers

DID

CLKODIV

SYS_IMSC

SYS_RIS

SYS_MIS

SYS_ICLR

SYS_TRIM

PLLCON

PCON

RSTCON

RSTSTAT

CLKCON

CLKSEL

CLKSTAT

APBCKSEL

IOMUX

AHBCKDIV

IOP00CFG

IOP01CFG

IOP04CFG

IOP05CFG

IOP06CFG

IOP07CFG

IOP10CFG

IOP12CFG

IOP13CFG

IOP14CFG

IOP15CFG

IOP16CFG

IOP17CFG

APBCKDIV

IOP21CFG

IOP22CFG

IOP23CFG

IOP24CFG

IOP25CFG

IOP26CFG

IOP30CFG

IOP31CFG

IOP32CFG

IOP34CFG

IOP35CFG

IOP36CFG

APBCKEN

IOP40CFG

IOP43CFG

IOP44CFG

IOP46CFG

IOP47CFG


DID

Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DID DID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSF DNO

DSF : Device Size of Flash Programming memory.
bits : 0 - 7 (8 bit)

Enumeration: ENUM

0x1C : 28K

28K

End of enumeration elements list.

DNO : Device number
bits : 16 - 47 (32 bit)


CLKODIV

Clock Output pin Division Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKODIV CLKODIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV EN CLK_SEL

DIV : Clock output divider values
bits : 0 - 7 (8 bit)

EN : Clock output enable
bits : 8 - 16 (9 bit)

Enumeration: ENUM

0 : disable

disable

1 : enable

enable

End of enumeration elements list.

CLK_SEL : CLK source select
bits : 9 - 19 (11 bit)

Enumeration: ENUM

0 : HCLK

HCLK

1 : IHRC

IHRC

2 : XT

XT

3 : PLLCLK

PLLCLK

End of enumeration elements list.


SYS_IMSC

Clock Interrupt control register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IMSC SYS_IMSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XT_IMSC PLL_IMSC

XT_IMSC : XT clock interrupt enable bit
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : disable

disable

1 : enable

enable

End of enumeration elements list.

PLL_IMSC : PLL clock interrupt enable bit
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : disable

disable

1 : enable

enable

End of enumeration elements list.


SYS_RIS

Clock interrupt source register
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYS_RIS SYS_RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XT_RIS PLL_RIS

XT_RIS : XT clock source interrupt status
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : 0

0

1 : 1

1

End of enumeration elements list.

PLL_RIS : PLL clock source interrupe status
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : 0

0

1 : 1

1

End of enumeration elements list.


SYS_MIS

Clock interrupt status register
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_MIS SYS_MIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XT_MIS PLL_MIS

XT_MIS : XT clock interrupt status bit
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : 0

0

1 : 1

1

End of enumeration elements list.

PLL_MIS : PLL clock interrupt status bit
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : 0

0

1 : 1

1

End of enumeration elements list.


SYS_ICLR

Clock interrupt clear register
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_ICLR SYS_ICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XT_ICLR PLL_ICLR

XT_ICLR : Clear XT clock interrupt status bit.
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : 0

no effect

1 : 1

clear xt interrupt status bit

End of enumeration elements list.

PLL_ICLR : Clear PLL cloce interupt status bit.
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : 0

no effect

1 : 1

clear xt interrupt status bit

End of enumeration elements list.


SYS_TRIM

IRC temper register
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_TRIM SYS_TRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PLLCON

PLL control register
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCON PLLCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN FIN_SEL FIN_DIV PLLSTB SEL_N OD N M BP

EN : PLL enable bit
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : disable

disable

1 : enable

enable

End of enumeration elements list.

FIN_SEL : PLL clock source select
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : IHRC

IHRC

1 : XT

XT

End of enumeration elements list.

FIN_DIV : FLL clock source div
bits : 2 - 5 (4 bit)

Enumeration: ENUM

0 : div 1

div 1

1 : div 2

div 2

2 : div 4

div 4

3 : div 8

div 8

End of enumeration elements list.

PLLSTB : PLL status bit
bits : 4 - 8 (5 bit)

Enumeration: ENUM

0 : not stable

not stable

1 : stable

stable

End of enumeration elements list.

SEL_N : PLL in source select
bits : 5 - 10 (6 bit)

Enumeration: ENUM

0 : N no effect

in clock = 1

1 : N effect

N effect

End of enumeration elements list.

OD : PLL out div
bits : 6 - 13 (8 bit)

N : PLL enable bit
bits : 8 - 21 (14 bit)

M : PLL enable bit
bits : 14 - 33 (20 bit)

BP : PLL bypass mode
bits : 20 - 40 (21 bit)

Enumeration: ENUM

0 : normal

normal

1 : Fin

Pll out is source

End of enumeration elements list.


PCON

Power Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCON PCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEPMODE DEEPSLEEP PowerDown

SLEEPMODE : sleep mode
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : disable

disable

1 : enable

enable

End of enumeration elements list.

DEEPSLEEP : deep sleep mode
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : disable

disable

1 : enable

enable

End of enumeration elements list.

PowerDown : power donw mode
bits : 2 - 4 (3 bit)

Enumeration: ENUM

0 : disable

disable

1 : enable

enable

End of enumeration elements list.


RSTCON

Reset Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

RSTCON RSTCON write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCURST CPURST

MCURST : MCU reset
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : Normal

Normal

1 : Reset MCU

Reset MCU, the Cortex-M0 CPU had issued the reset signal to reset the system by software writing 1

End of enumeration elements list.

CPURST : CPU kernel Reset (Set this bit will reset the Cortex-M0 CPU kernel and FMC, but it won reload Configuration)
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : Normal

Normal

1 : Reset CPU

Reset CPU

End of enumeration elements list.


RSTSTAT

Reset Status Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSTAT RSTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTRS MCURS CPURS

WDTRS : WDT Reset Status
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : 0

No WDT reset detected.

1 : 1

WDT reset detected.

End of enumeration elements list.

MCURS : MCU Reset Status
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : 0

No MCU reset detected.

1 : 1

MCU reset detected.

End of enumeration elements list.

CPURS : CPU Reset Status
bits : 3 - 6 (4 bit)

Enumeration: ENUM

0 : 0

No CPU reset detected.

1 : 1

CPU reset detected.

End of enumeration elements list.


CLKCON

Clock Source Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCON CLKCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRCSEL IRCEN XOSCEN XT_SEL XT_CHECK

IRCSEL : IRC Select
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : 32M

32M

1 : 22.1184M

22.1184M

End of enumeration elements list.

IRCEN : IRC enable bit
bits : 3 - 6 (4 bit)

Enumeration: ENUM

0 : disable

disable

1 : enable

enable

End of enumeration elements list.

XOSCEN : disable
bits : 4 - 8 (5 bit)

Enumeration: ENUM

0 : disable

disable

1 : enable

enable

End of enumeration elements list.

XT_SEL : XT clock select
bits : 5 - 10 (6 bit)

Enumeration: ENUM

0 : 32.768K

32.768K

1 : HS

HS

End of enumeration elements list.

XT_CHECK : XT check bit
bits : 6 - 12 (7 bit)

Enumeration: ENUM

0 : disable

disable

1 : enable

enable

End of enumeration elements list.


CLKSEL

Clock Source Select Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL CLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL

CLKSEL : Clock Source Select
bits : 0 - 1 (2 bit)

Enumeration: ENUM

0 : IRC

IRC is select

1 : XOSC

XOSC is select

2 : 10K

IRC 10KHz is select

3 : PLLCLK

PLLCLK is select

End of enumeration elements list.


CLKSTAT

Clock Source Status Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLKSTAT CLKSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRCSTB XOSCSTB

IRCSTB : Internal OSC Status
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : not stable

IRC is not stable or disable

1 : stable

IRC is stable.

End of enumeration elements list.

XOSCSTB : EXternal OSC Status
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : not stable

External OSC is not stable ordisable.

1 : stable

External OSC is stable.

End of enumeration elements list.


APBCKSEL

APB Clock Source Select Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBCKSEL APBCKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR01SEL

TMR01SEL : Timer 0/1 Clock Source Select
bits : 0 - 1 (2 bit)

Enumeration: ENUM

0 : PCLK

PCLK is select

0 : PCLK

PCLK is select

2 : XOSC

XOSC is select

3 : 10KHz

10KHz is select

End of enumeration elements list.


IOMUX

Read from User Configuration IOMUX
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IOMUX IOMUX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESETPORT XTALPORT

RESETPORT : External reset pin location
bits : 8 - 16 (9 bit)

Enumeration: ENUM

0 : enable

Enable external reset function.When external reset function enable, the reset pin will assign to P14 and P14 GPIO function MUX will disable.

1 : disable

Disable external reset function.

End of enumeration elements list.

XTALPORT : XTAL pin location
bits : 9 - 18 (10 bit)

Enumeration: ENUM

0 : GPIO function

P1.0/P1.1 assign to GPIO function.

1 : disable

P1.0/P1.1 assign to XTAL function.

End of enumeration elements list.


AHBCKDIV

AHB CLK Division Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBCKDIV AHBCKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHBDIV

AHBDIV : System AHB clock divider values
bits : 0 - 7 (8 bit)


IOP00CFG

GPIO P00 Configuration Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP00CFG IOP00CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : AN11

AN11

2 : TXD0

TXD0

3 : CTS0

CTS0

End of enumeration elements list.


IOP01CFG

GPIO P01 Configuration Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP01CFG IOP01CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : AN12

AN12

2 : RXD0

RXD0

3 : RTS0

RTS0

4 : SPI0_SS

SPI0_SS

End of enumeration elements list.


IOP04CFG

GPIO P04 Configuration Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP04CFG IOP04CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

3 : PWM3B

PWM3B

4 : SPI0_SS

SPI0_SS

End of enumeration elements list.


IOP05CFG

GPIO P05 Configuration Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP05CFG IOP05CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

3 : PWM3A

PWM3A

4 : SPI0_MOSI

SPI0_MOSI

End of enumeration elements list.


IOP06CFG

GPIO P06 Configuration Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP06CFG IOP06CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

3 : PWM2B

PWM2B

4 : SPI0_MISO

SPI0_MISO

End of enumeration elements list.


IOP07CFG

GPIO P07 Configuration Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP07CFG IOP07CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

3 : PWM2A

PWM2A

4 : SPI0_CLK

SPI0_CLK

End of enumeration elements list.


IOP10CFG

GPIO P10 Configuration Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP10CFG IOP10CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : AN1

AN1

End of enumeration elements list.


IOP12CFG

GPIO P12 Configuration Register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP12CFG IOP12CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : AN2

AN2

2 : RXD0

RXD0

3 : PWM0A

PWM0A

End of enumeration elements list.


IOP13CFG

GPIO P13 Configuration Register
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP13CFG IOP13CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : AN3

AN3

2 : TXD0

TXD0

3 : PWM0B

PWM0B

End of enumeration elements list.


IOP14CFG

GPIO P14 Configuration Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP14CFG IOP14CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : AN4

AN4

2 : RXD1

RXD1

3 : PWM2A

PWM2A

End of enumeration elements list.


IOP15CFG

GPIO P15 Configuration Register
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP15CFG IOP15CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : AN5

AN5

2 : TXD1

TXD1

3 : PWM2B

PWM2B

End of enumeration elements list.


IOP16CFG

GPIO P16 Configuration Register
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP16CFG IOP16CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : OSCI

OSCI

2 : RXD0

RXD0

3 : SCL0

SCL0

End of enumeration elements list.


IOP17CFG

GPIO P17 Configuration Register
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP17CFG IOP17CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : OSCO

OSCO

2 : TXD0

TXD0

3 : SDA0

SDA0

End of enumeration elements list.


APBCKDIV

APB CLK Division Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBCKDIV APBCKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APBDIV

APBDIV : System APB clock divider values
bits : 0 - 7 (8 bit)


IOP21CFG

GPIO P21 Configuration Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP21CFG IOP21CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

End of enumeration elements list.


IOP22CFG

GPIO P22 Configuration Register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP22CFG IOP22CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

2 : SCL0

SCL0

3 : PWM0A

PWM0A

4 : CTS1

CTS1

End of enumeration elements list.


IOP23CFG

GPIO P23 Configuration Register
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP23CFG IOP23CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

2 : SDA0

SDA0

3 : PWM0B

PWM0B

4 : RTS1

RTS1

End of enumeration elements list.


IOP24CFG

GPIO P24 Configuration Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP24CFG IOP24CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

2 : RXD1

RXD1

3 : PWM1A

PWM1A

End of enumeration elements list.


IOP25CFG

GPIO P25 Configuration Register
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP25CFG IOP25CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

2 : TXD1

TXD1

3 : PWM1B

PWM1B

End of enumeration elements list.


IOP26CFG

GPIO P26 Configuration Register
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP26CFG IOP26CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

3 : PWM2A

PWM2A

End of enumeration elements list.


IOP30CFG

GPIO P30 Configuration Register
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP30CFG IOP30CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : AN6

AN6

3 : PWM0A

PWM0A

End of enumeration elements list.


IOP31CFG

GPIO P31 Configuration Register
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP31CFG IOP31CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : AN7

AN7

3 : PWM0B

PWM0B

End of enumeration elements list.


IOP32CFG

GPIO P32 Configuration Register
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP32CFG IOP32CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : AN8

AN8

End of enumeration elements list.


IOP34CFG

GPIO P34 Configuration Register
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP34CFG IOP34CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

2 : SDA0

SDA0

3 : PWM3A

PWM3A

End of enumeration elements list.


IOP35CFG

GPIO P35 Configuration Register
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP35CFG IOP35CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

1 : AN10

AN10

2 : SCL0

SCL0

3 : PWM3B

PWM3B

End of enumeration elements list.


IOP36CFG

GPIO P36 Configuration Register
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP36CFG IOP36CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

3 : HCLKO

HCLKO

End of enumeration elements list.


APBCKEN

APB CLK Enable Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBCKEN APBCKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTCE TIMER01CE UART0CE UART1CE I2C0CE I2C1CE SSP0CE ADCCE PWMCE

WDTCE : WDT PCLK Enable
bits : 0 - 0 (1 bit)

Enumeration: ENUM

0 : Disable

Disable

1 : Enable

Enable

End of enumeration elements list.

TIMER01CE : TIMER01 PCLK Enable
bits : 1 - 2 (2 bit)

Enumeration: ENUM

0 : Disable

Disable

1 : Enable

Enable

End of enumeration elements list.

UART0CE : UART0 PCLK Enable
bits : 3 - 6 (4 bit)

Enumeration: ENUM

0 : Disable

Disable

1 : Enable

Enable

End of enumeration elements list.

UART1CE : UART1 PCLK Enable
bits : 4 - 8 (5 bit)

Enumeration: ENUM

0 : Disable

Disable

1 : Enable

Enable

End of enumeration elements list.

I2C0CE : I2C0 PCLK Enable
bits : 7 - 14 (8 bit)

Enumeration: ENUM

0 : Disable

Disable

1 : Enable

Enable

End of enumeration elements list.

I2C1CE : I2C1 PCLK Enable
bits : 8 - 16 (9 bit)

Enumeration: ENUM

0 : Disable

Disable

1 : Enable

Enable

End of enumeration elements list.

SSP0CE : SSP0 PCLK Enable
bits : 9 - 18 (10 bit)

Enumeration: ENUM

0 : Disable

Disable

1 : Enable

Enable

End of enumeration elements list.

ADCCE : ADC PCLK Enable
bits : 11 - 22 (12 bit)

Enumeration: ENUM

0 : Disable

Disable

1 : Enable

Enable

End of enumeration elements list.

PWMCE : Capture/PWM PCLK Enable
bits : 12 - 24 (13 bit)

Enumeration: ENUM

0 : Disable

Disable

1 : Enable

Enable

End of enumeration elements list.


IOP40CFG

GPIO P40 Configuration Register
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP40CFG IOP40CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

End of enumeration elements list.


IOP43CFG

GPIO P43 Configuration Register
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP43CFG IOP43CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

End of enumeration elements list.


IOP44CFG

GPIO P44 Configuration Register
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP44CFG IOP44CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

End of enumeration elements list.


IOP46CFG

GPIO P46 Configuration Register
address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP46CFG IOP46CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

2 : RXD1

RXD1

End of enumeration elements list.


IOP47CFG

GPIO P47 Configuration Register
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOP47CFG IOP47CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFG

CFG : Pxx function config
bits : 0 - 2 (3 bit)

Enumeration: ENUM

0 : GPIO

GPIO

2 : TXD1

TXD1

End of enumeration elements list.



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