Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection :
Clock operaton Mode Control Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMPH : Control of X1 clock oscillation frequency
bits : 0 - 0 (1 bit)
access : read-write
AMPHS : Control of XT1 clock oscillation frequency
bits : 1 - 3 (3 bit)
access : read-write
OSCSELS : Sub OSC Select
bits : 4 - 8 (5 bit)
access : read-write
EXCLKS : External Clock input mode
bits : 5 - 10 (6 bit)
access : read-write
OSCSEL : Main OSC Select
bits : 6 - 12 (7 bit)
access : read-write
EXCLK : External Clock input mode
bits : 7 - 14 (8 bit)
access : read-write
Clock operation Status Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIOSTOP : High-speed on-chip oscillator clock operation control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : START
High-speed on-chip oscillator operating
1 : STOP
High-speed on-chip oscillator stopped
End of enumeration elements list.
XTSTOP : Subsystem clock operation control
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : START
XT1 oscillator operating or External clock from EXCLKS pin is valid
1 : STOP
XT1 oscillator stop or External clock from EXCLKS pin is invalid
End of enumeration elements list.
MSTOP : High-speed system clock operation control
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : START
X1 oscillator operating or External clock from EXCLK pin is valid
1 : STOP
X1 oscillator stop or External clock from EXCLK pin is invalid
End of enumeration elements list.
High-speed on-chip oscillator trimming register
address_offset : 0x1800 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
High-speed on-chip oscillator frequency select register
address_offset : 0x1820 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Oscillation stabilization time counter status
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Peripheral enable register 0
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TM40EN : Control of the TM40 input clock
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disabled
Disables input clock supply
1 : Enable
Enables input clock supply
End of enumeration elements list.
TM41EN : Control of the TM41 input clock
bits : 1 - 2 (2 bit)
Enumeration:
0 : Disabled
Disables input clock supply
1 : Enable
Enables input clock supply
End of enumeration elements list.
SCI0EN : Control of the SCI0 input clock
bits : 2 - 4 (3 bit)
Enumeration:
0 : Disabled
Disables input clock supply
1 : Enable
Enables input clock supply
End of enumeration elements list.
SCI1EN : Control of the SCI1 input clock
bits : 3 - 6 (4 bit)
Enumeration:
0 : Disabled
Disables input clock supply
1 : Enable
Enables input clock supply
End of enumeration elements list.
IICA0EN : Control of the IICA0 input clock
bits : 4 - 8 (5 bit)
Enumeration:
0 : Disabled
Disables input clock supply
1 : Enable
Enables input clock supply
End of enumeration elements list.
ADCEN : Control of the ADC input clock
bits : 5 - 10 (6 bit)
Enumeration:
0 : Disabled
Disables input clock supply
1 : Enable
Enables input clock supply
End of enumeration elements list.
IRDAEN : Control of the IRDA input clock
bits : 6 - 12 (7 bit)
Enumeration:
0 : Disabled
Disables input clock supply
1 : Enable
Enables input clock supply
End of enumeration elements list.
RTCEN : Control of the RTC input clock
bits : 7 - 14 (8 bit)
Enumeration:
0 : Disabled
Disables input clock supply
1 : Enable
Enables input clock supply
End of enumeration elements list.
Subsystem clock supply mode control register
address_offset : 0x23 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WUTMMCK0 : Selection of operation clock for real-time clock, 15-bit interval timer
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : fSUB
The subsystem clock is selected as the operation clock for the real-time clock and the 15-bit interval timer. The low-speed on-chip oscillator cannot be selected as the count source for timer A.
1 : fIL
The low-speed on-chip oscillator clock is selected as the operation clock for the real-time clock and the 15-bit interval timer. Either the low-speed on-chip oscillator or the subsystem clock can be selected as the count source for timer A.
End of enumeration elements list.
RTCLPC : Setting in DEEPSLEEP mode or SLEEP mode while subsystem clock is selected as CPU clock
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Enable
Enables supply of subsystem clock to peripheral function
1 : Disable
Stops supply of subsystem clock to peripheral functions other than real-time clock and 15-bit interval timer.
End of enumeration elements list.
Oscillation stabilization time select register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
System clock control register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCM0 : Main system clock (fMAIN) operation control
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : fIH
Select the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN)
1 : fMX
Select the high-speed system clock (fMX) as the main system clock (fMAIN)
End of enumeration elements list.
MCS : Status of Main system clock (fMAIN)
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
0 : fIH
High-speed on-chip oscillator clock (fIH)
1 : fMX
High-speed system clock (fMX)
End of enumeration elements list.
CSS : Selection of CPU/peripheral hardware clock (fCLK)
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : fMAIN
Main system clock (fMAIN)
1 : fSUB
Subsystem clock (fSUB)
End of enumeration elements list.
CLS : Status of CPU/peripheral hardware clock (fCLK)
bits : 7 - 14 (8 bit)
access : read-only
Enumeration:
0 : fMAIN
Main system clock (fMAIN)
1 : fSUB
Subsystem clock (fSUB)
End of enumeration elements list.
Peripheral enable register 1
address_offset : 0x41A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : Control of the DMA input clock
bits : 3 - 6 (4 bit)
Enumeration:
0 : Disabled
Disables input clock supply
1 : Enable
Enables input clock supply
End of enumeration elements list.
CMPEN : Control of the CMP input clock
bits : 5 - 10 (6 bit)
Enumeration:
0 : Disabled
Disables input clock supply
1 : Enable
Enables input clock supply
End of enumeration elements list.
LOCO Frequency Select register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOSCSEL : LOCO Frequency Select
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disabled
LOCO's Frequency is 15K
1 : Enable
LOCO's Frequency is 30K
End of enumeration elements list.
LOSCSEL's Protect register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET mask register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTM : RESET mask
bits : 0 - 0 (1 bit)
Enumeration:
0 : Disabled
P00 is reset function
1 : Enable
P00 is GPIO input function
End of enumeration elements list.
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