\n

UART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

DATA

BAUDDIV

STATE

CTRL

INTSTATUS

INTCLEAR


DATA

Recieve and Transmit Data Value
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

BAUDDIV

Baudrate Divider
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BAUDDIV BAUDDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

STATE

UART Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATE STATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBF RXBF TXOV RXOV

TXBF : TX Buffer Full
bits : 0 - 0 (1 bit)
access : read-only

RXBF : RX Buffer Full
bits : 1 - 2 (2 bit)
access : read-only

TXOV : TX Buffer Overrun (write 1 to clear)
bits : 2 - 4 (3 bit)

RXOV : RX Buffer Overrun (write 1 to clear)
bits : 3 - 6 (4 bit)
access : read-write


CTRL

UART Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEN RXEN TXINT RXINT TXOVINT RVOVINT HSTX

TXEN : TX Enable
bits : 0 - 0 (1 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

RXEN : RX Enable
bits : 1 - 2 (2 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

TXINT : TX Interrupt Enable
bits : 2 - 4 (3 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

RXINT : RX Interrupt Enable
bits : 3 - 6 (4 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

TXOVINT : TX Overrun Interrupt Enable
bits : 4 - 8 (5 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

RVOVINT : RX Overrun Interrupt Enable
bits : 5 - 10 (6 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

HSTX : High Speed Test Mode for TX only
bits : 6 - 12 (7 bit)

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.


INTSTATUS

UART Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS INTSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINT RXINT TXOV RXOV

TXINT : TX Interrupt
bits : 0 - 0 (1 bit)

RXINT : RX Interrupt
bits : 1 - 2 (2 bit)

TXOV : TX Overrun Interrupt
bits : 2 - 4 (3 bit)

RXOV : RX Overrun Interrupt
bits : 3 - 6 (4 bit)


INTCLEAR

UART Interrupt CLEAR Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
alternate_register : INTSTATUS
reset_Mask : 0x0

INTCLEAR INTCLEAR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINT RXINT TXOV RXOV

TXINT : TX Interrupt
bits : 0 - 0 (1 bit)

RXINT : RX Interrupt
bits : 1 - 2 (2 bit)

TXOV : TX Overrun Interrupt
bits : 2 - 4 (3 bit)

RXOV : RX Overrun Interrupt
bits : 3 - 6 (4 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.