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PWM1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

PWM1CR

PRD1

DT1

TMR1

PWM2CR

PRD2

DT2

TMR2

PWM3CR

PRD3

DT3

TMR3

PWMENCR


PWM1CR

PWM1 Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM1CR PWM1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM1OSM PWM1DSFCL PWM1PSFCL T1P PWM1A PWM1E PWM1DSF PWM1PSF

PWM1OSM : One-shot mode of PWM. T1EN would be disable by HW when period match first time.
bits : 3 - 6 (4 bit)

PWM1DSFCL : Clear bit of PWM1 period-matching status flag
bits : 6 - 12 (7 bit)

PWM1PSFCL : Clear bit of PWM1 duty-matching status flag
bits : 7 - 14 (8 bit)
access : write-only

T1P : TimerA clock pre-scale option bits
bits : 8 - 18 (11 bit)
access : read-write

PWM1A : Active level of PWM1
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : High

Duty duration is logic high

1 : Low

Duty duration is logic low

End of enumeration elements list.

PWM1E : Compound pin
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

PWM1DSF : Status flag of duty-matching for PWM1. Read only.
bits : 16 - 32 (17 bit)
access : read-only

PWM1PSF : Status flag of period-matching for PWM1. Read only.
bits : 17 - 34 (18 bit)
access : read-only


PRD1

PWM1 Period
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRD1 PRD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRD1

PRD1 : PWM1 Period
bits : 0 - 15 (16 bit)
access : read-write


DT1

PWM1 Duty
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT1 DT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT1

DT1 : PWM1 Duty
bits : 0 - 15 (16 bit)
access : read-write


TMR1

Timer 1
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR1 TMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR1

TMR1 : Timer 1
bits : 0 - 15 (16 bit)
access : read-only


PWM2CR

PWM2 Control Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2CR PWM2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM2OSM PWM2DSFCL PWM2PSFCL T2P PWM2A PWM2E PWM2DSF PWM2PSF

PWM2OSM : One-shot mode of PWM. T2EN would be disable by HW when period match first time.
bits : 3 - 6 (4 bit)

PWM2DSFCL : Clear bit of PWM2 period-matching status flag
bits : 6 - 12 (7 bit)

PWM2PSFCL : Clear bit of PWM2 duty-matching status flag
bits : 7 - 14 (8 bit)
access : write-only

T2P : TimerA clock pre-scale option bits
bits : 8 - 18 (11 bit)
access : read-write

PWM2A : Active level of PWM2
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : High

Duty duration is logic high

1 : Low

Duty duration is logic low

End of enumeration elements list.

PWM2E : Compound pin
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

PWM2DSF : Status flag of duty-matching for PWM2. Read only.
bits : 16 - 32 (17 bit)
access : read-only

PWM2PSF : Status flag of period-matching for PWM2. Read only.
bits : 17 - 34 (18 bit)
access : read-only


PRD2

PWM2 Period
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRD2 PRD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRD2

PRD2 : PWM2 Period
bits : 0 - 15 (16 bit)
access : read-write


DT2

PWM2 Duty
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT2 DT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT2

DT2 : PWM2 Duty
bits : 0 - 15 (16 bit)
access : read-write


TMR2

Timer 2
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR2 TMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR2

TMR2 : Timer 2
bits : 0 - 15 (16 bit)
access : read-only


PWM3CR

PWM3 Control Register
address_offset : 0x300 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM3CR PWM3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM3OSM PWM3DSFCL PWM3PSFCL T3P PWM3A PWM3E PWM3DSF PWM3PSF

PWM3OSM : One-shot mode of PWM. T3EN would be disable by HW when period match first time.
bits : 3 - 6 (4 bit)

PWM3DSFCL : Clear bit of PWM3 period-matching status flag
bits : 6 - 12 (7 bit)

PWM3PSFCL : Clear bit of PWM3 duty-matching status flag
bits : 7 - 14 (8 bit)
access : write-only

T3P : TimerA clock pre-scale option bits
bits : 8 - 18 (11 bit)
access : read-write

PWM3A : Active level of PWM3
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : High

Duty duration is logic high

1 : Low

Duty duration is logic low

End of enumeration elements list.

PWM3E : Compound pin
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

PWM3DSF : Status flag of duty-matching for PWM3. Read only.
bits : 16 - 32 (17 bit)
access : read-only

PWM3PSF : Status flag of period-matching for PWM3. Read only.
bits : 17 - 34 (18 bit)
access : read-only


PRD3

PWM3 Period
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRD3 PRD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRD3

PRD3 : PWM3 Period
bits : 0 - 15 (16 bit)
access : read-write


DT3

PWM3 Duty
address_offset : 0x308 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DT3 DT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT3

DT3 : PWM3 Duty
bits : 0 - 15 (16 bit)
access : read-write


TMR3

Timer 3
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMR3 TMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR3

TMR3 : Timer 3
bits : 0 - 15 (16 bit)
access : read-only


PWMENCR

PWM Enable Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMENCR PWMENCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxEN PWM1DTIE PWM1PRDIE PWM2DTIE PWM2PRDIE PWM3DTIE PWM3PRDIE

TxEN : TMRX enable bit
bits : 0 - 2 (3 bit)

PWM1DTIE : Enable
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

0 : Disable

PWM1 Duty interrup disabled

1 : Enable

PWM1 Duty interrup enabled

End of enumeration elements list.

PWM1PRDIE : Enable
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

0 : Disable

PWM1 Period interrupt disabled

1 : Enable

PWM1 Period interrupt enabled

End of enumeration elements list.

PWM2DTIE : Enable
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

0 : Disable

PWM2 Duty interrup disabled

1 : Enable

PWM2 Duty interrup enabled

End of enumeration elements list.

PWM2PRDIE : Enable
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

0 : Disable

PWM2 Period interrupt disabled

1 : Enable

PWM2 Period interrupt enabled

End of enumeration elements list.

PWM3DTIE : Enable
bits : 14 - 28 (15 bit)
access : read-write

Enumeration:

0 : Disable

PWM3 Duty interrup disabled

1 : Enable

PWM3 Duty interrup enabled

End of enumeration elements list.

PWM3PRDIE : Enable
bits : 15 - 30 (16 bit)
access : read-write

Enumeration:

0 : Disable

PWM3 Period interrupt disabled

1 : Enable

PWM3 Period interrupt enabled

End of enumeration elements list.



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