\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
USART control register 1
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXE : Enable Receive Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
TXE : Enable Transmission Bit
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
STOP : Select Stop Bit
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : 1
1 Stop bit
1 : 2
2 Stop bit
End of enumeration elements list.
PRE : Enable Parity Addition Bit
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
EVEN : Select Parity Check Bit
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Odd
Odd parity
1 : Even
Even Parity
End of enumeration elements list.
UMODE : USART mode select bit
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : 8
8 Data bit
1 : 9
9 Data bit
End of enumeration elements list.
URINVEN : Enable UART TXD and RXD Port Inverse Output Bit
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
URDG : USART deglitch time select bits
bits : 9 - 19 (11 bit)
access : read-write
Enumeration:
0 : 00
50ns
1 : 01
200ns
2 : 10
400ns
3 : 11
Bypass
End of enumeration elements list.
USART baud rate register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USART control register 2
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPHA : Clock phase.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : middle
USART_CK toggle starts at the middle of first data bit
1 : beginning
USART_CK toggle starts at the beginning of first data bit.
End of enumeration elements list.
CPOL : Clock polarity
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : low
UASRT_CK active low
1 : high
UASRT_CK active high
End of enumeration elements list.
CLKEN : Clock enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
EIE : Error interrupt enable (Overrun, Frame, Noise)
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
PEIE : Parity error interrupt enable
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
RBFIE : Receiver buffer full interrupt enable
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
TSFIE : Transmit interrupt enable
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
TBIE : Transfer buffer empty interrupt enable
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : Disable
Disabled
1 : Enable
Enabled
End of enumeration elements list.
USART status register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NERR : Noise Error Flag.
bits : 0 - 0 (1 bit)
FMERR : Framing Error Flag.
bits : 1 - 2 (2 bit)
OVERR : Running Error Flag.
bits : 2 - 4 (3 bit)
PERR : Parity Error Flag.
bits : 3 - 6 (4 bit)
RBF : USART Read Buffer Full Flag.
bits : 5 - 10 (6 bit)
TSF : USART transmit status Flag.
bits : 6 - 12 (7 bit)
TBE : USART Transfer Buffer Empty Flag.
bits : 7 - 14 (8 bit)
USART transmit data buffer register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
alternate_register : USARTTD
reset_Mask : 0x0
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