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USART

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :

Registers

USARTCR1

USARTBR

USARTCR2

USARTSR

USARTTD


USARTCR1

USART control register 1
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USARTCR1 USARTCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXE TXE STOP PRE EVEN UMODE URINVEN URDG

RXE : Enable Receive Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

TXE : Enable Transmission Bit
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

STOP : Select Stop Bit
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : 1

1 Stop bit

1 : 2

2 Stop bit

End of enumeration elements list.

PRE : Enable Parity Addition Bit
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

EVEN : Select Parity Check Bit
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : Odd

Odd parity

1 : Even

Even Parity

End of enumeration elements list.

UMODE : USART mode select bit
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : 8

8 Data bit

1 : 9

9 Data bit

End of enumeration elements list.

URINVEN : Enable UART TXD and RXD Port Inverse Output Bit
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

URDG : USART deglitch time select bits
bits : 9 - 19 (11 bit)
access : read-write

Enumeration:

0 : 00

50ns

1 : 01

200ns

2 : 10

400ns

3 : 11

Bypass

End of enumeration elements list.


USARTBR

USART baud rate register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

USARTBR USARTBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

USARTCR2

USART control register 2
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USARTCR2 USARTCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL CLKEN EIE PEIE RBFIE TSFIE TBIE

CPHA : Clock phase.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : middle

USART_CK toggle starts at the middle of first data bit

1 : beginning

USART_CK toggle starts at the beginning of first data bit.

End of enumeration elements list.

CPOL : Clock polarity
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : low

UASRT_CK active low

1 : high

UASRT_CK active high

End of enumeration elements list.

CLKEN : Clock enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

EIE : Error interrupt enable (Overrun, Frame, Noise)
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

PEIE : Parity error interrupt enable
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

RBFIE : Receiver buffer full interrupt enable
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

TSFIE : Transmit interrupt enable
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.

TBIE : Transfer buffer empty interrupt enable
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

0 : Disable

Disabled

1 : Enable

Enabled

End of enumeration elements list.


USARTSR

USART status register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

USARTSR USARTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NERR FMERR OVERR PERR RBF TSF TBE

NERR : Noise Error Flag.
bits : 0 - 0 (1 bit)

FMERR : Framing Error Flag.
bits : 1 - 2 (2 bit)

OVERR : Running Error Flag.
bits : 2 - 4 (3 bit)

PERR : Parity Error Flag.
bits : 3 - 6 (4 bit)

RBF : USART Read Buffer Full Flag.
bits : 5 - 10 (6 bit)

TSF : USART transmit status Flag.
bits : 6 - 12 (7 bit)

TBE : USART Transfer Buffer Empty Flag.
bits : 7 - 14 (8 bit)


USARTTD

USART transmit data buffer register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
alternate_register : USARTTD
reset_Mask : 0x0

USARTTD USARTTD read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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