\n
address_offset : 0x0 Bytes (0x0)
size : 0x33D byte (0x0)
mem_usage : registers
protection :
Interrupt Set Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : SETENA
bits : 0 - 31 (32 bit)
Interrupt Set-Pending Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : SETPEND
bits : 0 - 31 (32 bit)
Interrupt Clear-Pending Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : CLRPEND
bits : 0 - 31 (32 bit)
Interrupt Priority Register 0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_00 : PRI_00
bits : 6 - 7 (2 bit)
PRI_01 : PRI_01
bits : 14 - 15 (2 bit)
PRI_02 : PRI_02
bits : 22 - 23 (2 bit)
PRI_03 : PRI_03
bits : 30 - 31 (2 bit)
Interrupt Priority Register 1
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_40 : PRI_40
bits : 6 - 7 (2 bit)
PRI_41 : PRI_41
bits : 14 - 15 (2 bit)
PRI_42 : PRI_42
bits : 22 - 23 (2 bit)
PRI_43 : PRI_43
bits : 30 - 31 (2 bit)
Interrupt Priority Register 2
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_80 : PRI_80
bits : 6 - 7 (2 bit)
PRI_81 : PRI_81
bits : 14 - 15 (2 bit)
PRI_82 : PRI_82
bits : 22 - 23 (2 bit)
PRI_83 : PRI_83
bits : 30 - 31 (2 bit)
Interrupt Priority Register 3
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_120 : PRI_120
bits : 6 - 7 (2 bit)
PRI_121 : PRI_121
bits : 14 - 15 (2 bit)
PRI_122 : PRI_122
bits : 22 - 23 (2 bit)
PRI_123 : PRI_123
bits : 30 - 31 (2 bit)
Interrupt Priority Register 4
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_160 : PRI_160
bits : 6 - 7 (2 bit)
PRI_161 : PRI_161
bits : 14 - 15 (2 bit)
PRI_162 : PRI_162
bits : 22 - 23 (2 bit)
PRI_163 : PRI_163
bits : 30 - 31 (2 bit)
Interrupt Priority Register 5
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_200 : PRI_200
bits : 6 - 7 (2 bit)
PRI_201 : PRI_201
bits : 14 - 15 (2 bit)
PRI_202 : PRI_202
bits : 22 - 23 (2 bit)
PRI_203 : PRI_203
bits : 30 - 31 (2 bit)
Interrupt Priority Register 6
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_240 : PRI_240
bits : 6 - 7 (2 bit)
PRI_241 : PRI_241
bits : 14 - 15 (2 bit)
PRI_242 : PRI_242
bits : 22 - 23 (2 bit)
PRI_243 : PRI_243
bits : 30 - 31 (2 bit)
Interrupt Priority Register 7
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_280 : PRI_280
bits : 6 - 7 (2 bit)
PRI_281 : PRI_281
bits : 14 - 15 (2 bit)
PRI_282 : PRI_282
bits : 22 - 23 (2 bit)
PRI_283 : PRI_283
bits : 30 - 31 (2 bit)
Interrupt Clear Enable Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : CLRENA
bits : 0 - 31 (32 bit)
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