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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR

APB1RSTR

AHBENR

APB2ENR

APB1ENR

BDCR

CSR

AHBRSTR

CFGR2

CFGR3

CR2

CFGR

CIR

APB2RSTR


CR

Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSION HSIRDY HSITRIM HSICAL HSEON HSERDY HSEBYP CSSON PLLON PLLRDY

HSION : Internal High Speed clock enable
bits : 0 - 0 (1 bit)
access : read-write

HSIRDY : Internal High Speed clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

HSITRIM : Internal High Speed clock trimming
bits : 3 - 7 (5 bit)
access : read-write

HSICAL : Internal High Speed clock Calibration
bits : 8 - 15 (8 bit)
access : read-only

HSEON : External High Speed clock enable
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : External High Speed clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HSEBYP : External High Speed clock Bypass
bits : 18 - 18 (1 bit)
access : read-write

CSSON : Clock Security System enable
bits : 19 - 19 (1 bit)
access : read-write

PLLON : PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLRDY : PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only


APB1RSTR

APB1 peripheral reset register (RCC_APB1RSTR)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR APB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2RST TIM3RST TIM6RST TIM7RST TIM14RST WWDGRST SPI2RST USART2RST USART3RST USART4RST I2C1RST I2C2RST USBRST CANRST CRSRST PWRRST DACRST CECRST

TIM2RST : Timer 2 reset
bits : 0 - 0 (1 bit)

TIM3RST : Timer 3 reset
bits : 1 - 1 (1 bit)

TIM6RST : Timer 6 reset
bits : 4 - 4 (1 bit)

TIM7RST : TIM7 timer reset
bits : 5 - 5 (1 bit)

TIM14RST : Timer 14 reset
bits : 8 - 8 (1 bit)

WWDGRST : Window watchdog reset
bits : 11 - 11 (1 bit)

SPI2RST : SPI2 reset
bits : 14 - 14 (1 bit)

USART2RST : USART 2 reset
bits : 17 - 17 (1 bit)

USART3RST : USART3 reset
bits : 18 - 18 (1 bit)

USART4RST : USART4 reset
bits : 19 - 19 (1 bit)

I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C2 reset
bits : 22 - 22 (1 bit)

USBRST : USB interface reset
bits : 23 - 23 (1 bit)

CANRST : CAN interface reset
bits : 25 - 25 (1 bit)

CRSRST : Clock Recovery System interface reset
bits : 27 - 27 (1 bit)

PWRRST : Power interface reset
bits : 28 - 28 (1 bit)

DACRST : DAC interface reset
bits : 29 - 29 (1 bit)

CECRST : HDMI CEC reset
bits : 30 - 30 (1 bit)


AHBENR

AHB Peripheral Clock enable register (RCC_AHBENR)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBENR AHBENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN SRAMEN FLITFEN CRCEN IOPAEN IOPBEN IOPCEN IOPDEN IOPFEN TSCEN

DMAEN : DMA1 clock enable
bits : 0 - 0 (1 bit)

SRAMEN : SRAM interface clock enable
bits : 2 - 2 (1 bit)

FLITFEN : FLITF clock enable
bits : 4 - 4 (1 bit)

CRCEN : CRC clock enable
bits : 6 - 6 (1 bit)

IOPAEN : I/O port A clock enable
bits : 17 - 17 (1 bit)

IOPBEN : I/O port B clock enable
bits : 18 - 18 (1 bit)

IOPCEN : I/O port C clock enable
bits : 19 - 19 (1 bit)

IOPDEN : I/O port D clock enable
bits : 20 - 20 (1 bit)

IOPFEN : I/O port F clock enable
bits : 22 - 22 (1 bit)

TSCEN : Touch sensing controller clock enable
bits : 24 - 24 (1 bit)


APB2ENR

APB2 peripheral clock enable register (RCC_APB2ENR)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2ENR APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGEN ADCEN TIM1EN SPI1EN USART1EN TIM15EN TIM16EN TIM17EN DBGMCUEN

SYSCFGEN : SYSCFG clock enable
bits : 0 - 0 (1 bit)

ADCEN : ADC 1 interface clock enable
bits : 9 - 9 (1 bit)

TIM1EN : TIM1 Timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI 1 clock enable
bits : 12 - 12 (1 bit)

USART1EN : USART1 clock enable
bits : 14 - 14 (1 bit)

TIM15EN : TIM15 timer clock enable
bits : 16 - 16 (1 bit)

TIM16EN : TIM16 timer clock enable
bits : 17 - 17 (1 bit)

TIM17EN : TIM17 timer clock enable
bits : 18 - 18 (1 bit)

DBGMCUEN : MCU debug module clock enable
bits : 22 - 22 (1 bit)


APB1ENR

APB1 peripheral clock enable register (RCC_APB1ENR)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR APB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN TIM3EN TIM6EN TIM7EN TIM14EN WWDGEN SPI2EN USART2EN USART3EN USART4EN I2C1EN I2C2EN USBRST CANEN CRSEN PWREN DACEN CECEN

TIM2EN : Timer 2 clock enable
bits : 0 - 0 (1 bit)

TIM3EN : Timer 3 clock enable
bits : 1 - 1 (1 bit)

TIM6EN : Timer 6 clock enable
bits : 4 - 4 (1 bit)

TIM7EN : TIM7 timer clock enable
bits : 5 - 5 (1 bit)

TIM14EN : Timer 14 clock enable
bits : 8 - 8 (1 bit)

WWDGEN : Window watchdog clock enable
bits : 11 - 11 (1 bit)

SPI2EN : SPI 2 clock enable
bits : 14 - 14 (1 bit)

USART2EN : USART 2 clock enable
bits : 17 - 17 (1 bit)

USART3EN : USART3 clock enable
bits : 18 - 18 (1 bit)

USART4EN : USART4 clock enable
bits : 19 - 19 (1 bit)

I2C1EN : I2C 1 clock enable
bits : 21 - 21 (1 bit)

I2C2EN : I2C 2 clock enable
bits : 22 - 22 (1 bit)

USBRST : USB interface clock enable
bits : 23 - 23 (1 bit)

CANEN : CAN interface clock enable
bits : 25 - 25 (1 bit)

CRSEN : Clock Recovery System interface clock enable
bits : 27 - 27 (1 bit)

PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)

DACEN : DAC interface clock enable
bits : 29 - 29 (1 bit)

CECEN : HDMI CEC interface clock enable
bits : 30 - 30 (1 bit)


BDCR

Backup domain control register (RCC_BDCR)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDCR BDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSEON LSERDY LSEBYP LSEDRV RTCSEL RTCEN BDRST

LSEON : External Low Speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSERDY : External Low Speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSEBYP : External Low Speed oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write

LSEDRV : LSE oscillator drive capability
bits : 3 - 4 (2 bit)
access : read-write

RTCSEL : RTC clock source selection
bits : 8 - 9 (2 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BDRST : Backup domain software reset
bits : 16 - 16 (1 bit)
access : read-write


CSR

Control/status register (RCC_CSR)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY RMVF OBLRSTF PINRSTF PORRSTF SFTRSTF IWDGRSTF WWDGRSTF LPWRRSTF

LSION : Internal low speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSIRDY : Internal low speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

RMVF : Remove reset flag
bits : 24 - 24 (1 bit)
access : read-write

OBLRSTF : Option byte loader reset flag
bits : 25 - 25 (1 bit)
access : read-write

PINRSTF : PIN reset flag
bits : 26 - 26 (1 bit)
access : read-write

PORRSTF : POR/PDR reset flag
bits : 27 - 27 (1 bit)
access : read-write

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-write

IWDGRSTF : Independent watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-write

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-write

LPWRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-write


AHBRSTR

AHB peripheral reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBRSTR AHBRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOPARST IOPBRST IOPCRST IOPDRST IOPFRST TSCRST

IOPARST : I/O port A reset
bits : 17 - 17 (1 bit)

IOPBRST : I/O port B reset
bits : 18 - 18 (1 bit)

IOPCRST : I/O port C reset
bits : 19 - 19 (1 bit)

IOPDRST : I/O port D reset
bits : 20 - 20 (1 bit)

IOPFRST : I/O port F reset
bits : 22 - 22 (1 bit)

TSCRST : Touch sensing controller reset
bits : 24 - 24 (1 bit)


CFGR2

Clock configuration register 2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREDIV

PREDIV : PREDIV division factor
bits : 0 - 3 (4 bit)


CFGR3

Clock configuration register 3
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR3 CFGR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USART1SW I2C1SW CECSW USBSW ADCSW USART2SW

USART1SW : USART1 clock source selection
bits : 0 - 1 (2 bit)

I2C1SW : I2C1 clock source selection
bits : 4 - 4 (1 bit)

CECSW : HDMI CEC clock source selection
bits : 6 - 6 (1 bit)

USBSW : USB clock source selection
bits : 7 - 7 (1 bit)

ADCSW : ADC clock source selection
bits : 8 - 8 (1 bit)

USART2SW : USART2 clock source selection
bits : 16 - 17 (2 bit)


CR2

Clock control register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSI14ON HSI14RDY HSI14DIS HSI14TRIM HSI14CAL HSI48ON HSI48RDY HSI48CAL

HSI14ON : HSI14 clock enable
bits : 0 - 0 (1 bit)
access : read-write

HSI14RDY : HR14 clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

HSI14DIS : HSI14 clock request from ADC disable
bits : 2 - 2 (1 bit)
access : read-write

HSI14TRIM : HSI14 clock trimming
bits : 3 - 7 (5 bit)
access : read-write

HSI14CAL : HSI14 clock calibration
bits : 8 - 15 (8 bit)
access : read-only

HSI48ON : HSI48 clock enable
bits : 16 - 16 (1 bit)
access : read-write

HSI48RDY : HSI48 clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HSI48CAL : HSI48 factory clock calibration
bits : 24 - 24 (1 bit)
access : read-only


CFGR

Clock configuration register (RCC_CFGR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS HPRE PPRE ADCPRE PLLSRC PLLXTPRE PLLMUL MCO MCOPRE PLLNODIV

SW : System clock Switch
bits : 0 - 1 (2 bit)
access : read-write

SWS : System Clock Switch Status
bits : 2 - 3 (2 bit)
access : read-only

HPRE : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write

PPRE : APB Low speed prescaler (APB1)
bits : 8 - 10 (3 bit)
access : read-write

ADCPRE : ADC prescaler
bits : 14 - 14 (1 bit)
access : read-write

PLLSRC : PLL input clock source
bits : 15 - 16 (2 bit)
access : read-write

PLLXTPRE : HSE divider for PLL entry
bits : 17 - 17 (1 bit)
access : read-write

PLLMUL : PLL Multiplication Factor
bits : 18 - 21 (4 bit)
access : read-write

MCO : Microcontroller clock output
bits : 24 - 26 (3 bit)
access : read-write

MCOPRE : Microcontroller Clock Output Prescaler
bits : 28 - 30 (3 bit)
access : read-write

PLLNODIV : PLL clock not divided for MCO
bits : 31 - 31 (1 bit)
access : read-write


CIR

Clock interrupt register (RCC_CIR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR CIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF LSERDYF HSIRDYF HSERDYF PLLRDYF HSI14RDYF HSI48RDYF CSSF LSIRDYIE LSERDYIE HSIRDYIE HSERDYIE PLLRDYIE HSI14RDYE HSI48RDYIE LSIRDYC LSERDYC HSIRDYC HSERDYC PLLRDYC HSI14RDYC HSI48RDYC CSSC

LSIRDYF : LSI Ready Interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

LSERDYF : LSE Ready Interrupt flag
bits : 1 - 1 (1 bit)
access : read-only

HSIRDYF : HSI Ready Interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

HSERDYF : HSE Ready Interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

PLLRDYF : PLL Ready Interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

HSI14RDYF : HSI14 ready interrupt flag
bits : 5 - 5 (1 bit)
access : read-only

HSI48RDYF : HSI48 ready interrupt flag
bits : 6 - 6 (1 bit)
access : read-only

CSSF : Clock Security System Interrupt flag
bits : 7 - 7 (1 bit)
access : read-only

LSIRDYIE : LSI Ready Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

LSERDYIE : LSE Ready Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

HSIRDYIE : HSI Ready Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

HSERDYIE : HSE Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

PLLRDYIE : PLL Ready Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

HSI14RDYE : HSI14 ready interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

HSI48RDYIE : HSI48 ready interrupt enable
bits : 14 - 14 (1 bit)
access : read-write

LSIRDYC : LSI Ready Interrupt Clear
bits : 16 - 16 (1 bit)
access : write-only

LSERDYC : LSE Ready Interrupt Clear
bits : 17 - 17 (1 bit)
access : write-only

HSIRDYC : HSI Ready Interrupt Clear
bits : 18 - 18 (1 bit)
access : write-only

HSERDYC : HSE Ready Interrupt Clear
bits : 19 - 19 (1 bit)
access : write-only

PLLRDYC : PLL Ready Interrupt Clear
bits : 20 - 20 (1 bit)
access : write-only

HSI14RDYC : HSI 14 MHz Ready Interrupt Clear
bits : 21 - 21 (1 bit)
access : write-only

HSI48RDYC : HSI48 Ready Interrupt Clear
bits : 22 - 22 (1 bit)
access : write-only

CSSC : Clock security system interrupt clear
bits : 23 - 23 (1 bit)
access : write-only


APB2RSTR

APB2 peripheral reset register (RCC_APB2RSTR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RSTR APB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCFGRST ADCRST TIM1RST SPI1RST USART1RST TIM15RST TIM16RST TIM17RST DBGMCURST

SYSCFGRST : SYSCFG and COMP reset
bits : 0 - 0 (1 bit)

ADCRST : ADC interface reset
bits : 9 - 9 (1 bit)

TIM1RST : TIM1 timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI 1 reset
bits : 12 - 12 (1 bit)

USART1RST : USART1 reset
bits : 14 - 14 (1 bit)

TIM15RST : TIM15 timer reset
bits : 16 - 16 (1 bit)

TIM16RST : TIM16 timer reset
bits : 17 - 17 (1 bit)

TIM17RST : TIM17 timer reset
bits : 18 - 18 (1 bit)

DBGMCURST : Debug MCU reset
bits : 22 - 22 (1 bit)



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