\n

SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CFGR1

EXTICR3

EXTICR4

CFGR2

EXTICR1

EXTICR2


CFGR1

configuration register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR1 CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM_MODE ADC_DMA_RMP USART1_TX_DMA_RMP USART1_RX_DMA_RMP TIM16_DMA_RMP TIM17_DMA_RMP I2C_PB6_FM I2C_PB7_FM I2C_PB8_FM I2C_PB9_FM I2C1_FM_plus I2C2_FM_plus SPI2_DMA_RMP USART2_DMA_RMP USART3_DMA_RMP I2C1_DMA_RMP TIM1_DMA_RMP TIM2_DMA_RMP TIM3_DMA_RMP

MEM_MODE : Memory mapping selection bits
bits : 0 - 1 (2 bit)

ADC_DMA_RMP : ADC DMA remapping bit
bits : 8 - 8 (1 bit)

USART1_TX_DMA_RMP : USART1_TX DMA remapping bit
bits : 9 - 9 (1 bit)

USART1_RX_DMA_RMP : USART1_RX DMA request remapping bit
bits : 10 - 10 (1 bit)

TIM16_DMA_RMP : TIM16 DMA request remapping bit
bits : 11 - 11 (1 bit)

TIM17_DMA_RMP : TIM17 DMA request remapping bit
bits : 12 - 12 (1 bit)

I2C_PB6_FM : Fast Mode Plus (FM plus) driving capability activation bits.
bits : 16 - 16 (1 bit)

I2C_PB7_FM : Fast Mode Plus (FM+) driving capability activation bits.
bits : 17 - 17 (1 bit)

I2C_PB8_FM : Fast Mode Plus (FM+) driving capability activation bits.
bits : 18 - 18 (1 bit)

I2C_PB9_FM : Fast Mode Plus (FM+) driving capability activation bits.
bits : 19 - 19 (1 bit)

I2C1_FM_plus : FM+ driving capability activation for I2C1
bits : 20 - 20 (1 bit)

I2C2_FM_plus : FM+ driving capability activation for I2C2
bits : 21 - 21 (1 bit)

SPI2_DMA_RMP : SPI2 DMA request remapping bit
bits : 24 - 24 (1 bit)

USART2_DMA_RMP : USART2 DMA request remapping bit
bits : 25 - 25 (1 bit)

USART3_DMA_RMP : USART3 DMA request remapping bit
bits : 26 - 26 (1 bit)

I2C1_DMA_RMP : I2C1 DMA request remapping bit
bits : 27 - 27 (1 bit)

TIM1_DMA_RMP : TIM1 DMA request remapping bit
bits : 28 - 28 (1 bit)

TIM2_DMA_RMP : TIM2 DMA request remapping bit
bits : 29 - 29 (1 bit)

TIM3_DMA_RMP : TIM3 DMA request remapping bit
bits : 30 - 30 (1 bit)


EXTICR3

external interrupt configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR3 EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8 EXTI9 EXTI10 EXTI11

EXTI8 : EXTI 8 configuration bits
bits : 0 - 3 (4 bit)

EXTI9 : EXTI 9 configuration bits
bits : 4 - 7 (4 bit)

EXTI10 : EXTI 10 configuration bits
bits : 8 - 11 (4 bit)

EXTI11 : EXTI 11 configuration bits
bits : 12 - 15 (4 bit)


EXTICR4

external interrupt configuration register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR4 EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12 EXTI13 EXTI14 EXTI15

EXTI12 : EXTI 12 configuration bits
bits : 0 - 3 (4 bit)

EXTI13 : EXTI 13 configuration bits
bits : 4 - 7 (4 bit)

EXTI14 : EXTI 14 configuration bits
bits : 8 - 11 (4 bit)

EXTI15 : EXTI 15 configuration bits
bits : 12 - 15 (4 bit)


CFGR2

configuration register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCUP_LOCK SRAM_PARITY_LOCK PVD_LOCK SRAM_PEF

LOCUP_LOCK : Cortex-M0 LOCKUP bit enable bit
bits : 0 - 0 (1 bit)

SRAM_PARITY_LOCK : SRAM parity lock bit
bits : 1 - 1 (1 bit)

PVD_LOCK : PVD lock enable bit
bits : 2 - 2 (1 bit)

SRAM_PEF : SRAM parity flag
bits : 8 - 8 (1 bit)


EXTICR1

external interrupt configuration register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR1 EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0 EXTI1 EXTI2 EXTI3

EXTI0 : EXTI 0 configuration bits
bits : 0 - 3 (4 bit)

EXTI1 : EXTI 1 configuration bits
bits : 4 - 7 (4 bit)

EXTI2 : EXTI 2 configuration bits
bits : 8 - 11 (4 bit)

EXTI3 : EXTI 3 configuration bits
bits : 12 - 15 (4 bit)


EXTICR2

external interrupt configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR2 EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4 EXTI5 EXTI6 EXTI7

EXTI4 : EXTI 4 configuration bits
bits : 0 - 3 (4 bit)

EXTI5 : EXTI 5 configuration bits
bits : 4 - 7 (4 bit)

EXTI6 : EXTI 6 configuration bits
bits : 8 - 11 (4 bit)

EXTI7 : EXTI 7 configuration bits
bits : 12 - 15 (4 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.