\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
interrupt and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRDY : ADC ready
bits : 0 - 0 (1 bit)
EOSMP : End of sampling flag
bits : 1 - 1 (1 bit)
EOC : End of conversion flag
bits : 2 - 2 (1 bit)
EOS : End of sequence flag
bits : 3 - 3 (1 bit)
OVR : ADC overrun
bits : 4 - 4 (1 bit)
AWD : Analog watchdog flag
bits : 7 - 7 (1 bit)
configuration register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
JITOFF_D2 : JITOFF_D2
bits : 30 - 30 (1 bit)
JITOFF_D4 : JITOFF_D4
bits : 31 - 31 (1 bit)
sampling time register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMPR : Sampling time selection
bits : 0 - 2 (3 bit)
watchdog threshold register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LT : Analog watchdog lower threshold
bits : 0 - 11 (12 bit)
HT : Analog watchdog higher threshold
bits : 16 - 27 (12 bit)
channel selection register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSEL0 : Channel-x selection
bits : 0 - 0 (1 bit)
CHSEL1 : Channel-x selection
bits : 1 - 1 (1 bit)
CHSEL2 : Channel-x selection
bits : 2 - 2 (1 bit)
CHSEL3 : Channel-x selection
bits : 3 - 3 (1 bit)
CHSEL4 : Channel-x selection
bits : 4 - 4 (1 bit)
CHSEL5 : Channel-x selection
bits : 5 - 5 (1 bit)
CHSEL6 : Channel-x selection
bits : 6 - 6 (1 bit)
CHSEL7 : Channel-x selection
bits : 7 - 7 (1 bit)
CHSEL8 : Channel-x selection
bits : 8 - 8 (1 bit)
CHSEL9 : Channel-x selection
bits : 9 - 9 (1 bit)
CHSEL10 : Channel-x selection
bits : 10 - 10 (1 bit)
CHSEL11 : Channel-x selection
bits : 11 - 11 (1 bit)
CHSEL12 : Channel-x selection
bits : 12 - 12 (1 bit)
CHSEL13 : Channel-x selection
bits : 13 - 13 (1 bit)
CHSEL14 : Channel-x selection
bits : 14 - 14 (1 bit)
CHSEL15 : Channel-x selection
bits : 15 - 15 (1 bit)
CHSEL16 : Channel-x selection
bits : 16 - 16 (1 bit)
CHSEL17 : Channel-x selection
bits : 17 - 17 (1 bit)
CHSEL18 : Channel-x selection
bits : 18 - 18 (1 bit)
common configuration register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREFEN : Temperature sensor and VREFINT enable
bits : 22 - 22 (1 bit)
TSEN : Temperature sensor enable
bits : 23 - 23 (1 bit)
VBATEN : VBAT enable
bits : 24 - 24 (1 bit)
interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADRDYIE : ADC ready interrupt enable
bits : 0 - 0 (1 bit)
EOSMPIE : End of sampling flag interrupt enable
bits : 1 - 1 (1 bit)
EOCIE : End of conversion interrupt enable
bits : 2 - 2 (1 bit)
EOSIE : End of conversion sequence interrupt enable
bits : 3 - 3 (1 bit)
OVRIE : Overrun interrupt enable
bits : 4 - 4 (1 bit)
AWDIE : Analog watchdog interrupt enable
bits : 7 - 7 (1 bit)
data register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Converted data
bits : 0 - 15 (16 bit)
control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADEN : ADC enable command
bits : 0 - 0 (1 bit)
ADDIS : ADC disable command
bits : 1 - 1 (1 bit)
ADSTART : ADC start conversion command
bits : 2 - 2 (1 bit)
ADSTP : ADC stop conversion command
bits : 4 - 4 (1 bit)
ADCAL : ADC calibration
bits : 31 - 31 (1 bit)
configuration register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : Direct memory access enable
bits : 0 - 0 (1 bit)
DMACFG : Direct memery access configuration
bits : 1 - 1 (1 bit)
SCANDIR : Scan sequence direction
bits : 2 - 2 (1 bit)
RES : Data resolution
bits : 3 - 4 (2 bit)
ALIGN : Data alignment
bits : 5 - 5 (1 bit)
EXTSEL : External trigger selection
bits : 6 - 8 (3 bit)
EXTEN : External trigger enable and polarity selection
bits : 10 - 11 (2 bit)
OVRMOD : Overrun management mode
bits : 12 - 12 (1 bit)
CONT : Single / continuous conversion mode
bits : 13 - 13 (1 bit)
AUTDLY : Auto-delayed conversion mode
bits : 14 - 14 (1 bit)
AUTOFF : Auto-off mode
bits : 15 - 15 (1 bit)
DISCEN : Discontinuous mode
bits : 16 - 16 (1 bit)
AWDSGL : Enable the watchdog on a single channel or on all channels
bits : 22 - 22 (1 bit)
AWDEN : Analog watchdog enable
bits : 23 - 23 (1 bit)
AWDCH : Analog watchdog channel selection
bits : 26 - 30 (5 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.