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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

TR

PRER

ALRMAR

WPR

SSR

SHIFTR

TSTR

TSDR

TSSSR

CALR

DR

TAFCR

ALRMASSR

BKP0R

BKP1R

BKP2R

BKP3R

BKP4R

CR

ISR


TR

time register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TR TR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SU ST MNU MNT HU HT PM

SU : Second units in BCD format
bits : 0 - 3 (4 bit)

ST : Second tens in BCD format
bits : 4 - 6 (3 bit)

MNU : Minute units in BCD format
bits : 8 - 11 (4 bit)

MNT : Minute tens in BCD format
bits : 12 - 14 (3 bit)

HU : Hour units in BCD format
bits : 16 - 19 (4 bit)

HT : Hour tens in BCD format
bits : 20 - 21 (2 bit)

PM : AM/PM notation
bits : 22 - 22 (1 bit)


PRER

prescaler register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRER PRER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREDIV_S PREDIV_A

PREDIV_S : Synchronous prescaler factor
bits : 0 - 14 (15 bit)

PREDIV_A : Asynchronous prescaler factor
bits : 16 - 22 (7 bit)


ALRMAR

alarm A register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALRMAR ALRMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SU ST MSK1 MNU MNT MSK2 HU HT PM MSK3 DU DT WDSEL MSK4

SU : Second units in BCD format.
bits : 0 - 3 (4 bit)

ST : Second tens in BCD format.
bits : 4 - 6 (3 bit)

MSK1 : Alarm A seconds mask
bits : 7 - 7 (1 bit)

MNU : Minute units in BCD format.
bits : 8 - 11 (4 bit)

MNT : Minute tens in BCD format.
bits : 12 - 14 (3 bit)

MSK2 : Alarm A minutes mask
bits : 15 - 15 (1 bit)

HU : Hour units in BCD format.
bits : 16 - 19 (4 bit)

HT : Hour tens in BCD format.
bits : 20 - 21 (2 bit)

PM : AM/PM notation
bits : 22 - 22 (1 bit)

MSK3 : Alarm A hours mask
bits : 23 - 23 (1 bit)

DU : Date units or day in BCD format.
bits : 24 - 27 (4 bit)

DT : Date tens in BCD format.
bits : 28 - 29 (2 bit)

WDSEL : Week day selection
bits : 30 - 30 (1 bit)

MSK4 : Alarm A date mask
bits : 31 - 31 (1 bit)


WPR

write protection register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WPR WPR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : Write protection key
bits : 0 - 7 (8 bit)


SSR

sub second register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSR SSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS

SS : Sub second value
bits : 0 - 15 (16 bit)


SHIFTR

shift control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SHIFTR SHIFTR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBFS ADD1S

SUBFS : Subtract a fraction of a second
bits : 0 - 14 (15 bit)

ADD1S : Reserved
bits : 31 - 31 (1 bit)


TSTR

timestamp time register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSTR TSTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SU ST MNU MNT HU HT PM

SU : Second units in BCD format.
bits : 0 - 3 (4 bit)

ST : Second tens in BCD format.
bits : 4 - 6 (3 bit)

MNU : Minute units in BCD format.
bits : 8 - 11 (4 bit)

MNT : Minute tens in BCD format.
bits : 12 - 14 (3 bit)

HU : Hour units in BCD format.
bits : 16 - 19 (4 bit)

HT : Hour tens in BCD format.
bits : 20 - 21 (2 bit)

PM : AM/PM notation
bits : 22 - 22 (1 bit)


TSDR

timestamp date register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSDR TSDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DU DT MU MT WDU

DU : Date units in BCD format
bits : 0 - 3 (4 bit)

DT : Date tens in BCD format
bits : 4 - 5 (2 bit)

MU : Month units in BCD format
bits : 8 - 11 (4 bit)

MT : Month tens in BCD format
bits : 12 - 12 (1 bit)

WDU : Week day units
bits : 13 - 15 (3 bit)


TSSSR

time-stamp sub second register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TSSSR TSSSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS

SS : Sub second value
bits : 0 - 15 (16 bit)


CALR

calibration register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALR CALR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALM CALW16 CALW8 CALP

CALM : Calibration minus
bits : 0 - 8 (9 bit)

CALW16 : Reserved
bits : 13 - 13 (1 bit)

CALW8 : Use a 16-second calibration cycle period
bits : 14 - 14 (1 bit)

CALP : Use an 8-second calibration cycle period
bits : 15 - 15 (1 bit)


DR

date register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DU DT MU MT WDU YU YT

DU : Date units in BCD format
bits : 0 - 3 (4 bit)

DT : Date tens in BCD format
bits : 4 - 5 (2 bit)

MU : Month units in BCD format
bits : 8 - 11 (4 bit)

MT : Month tens in BCD format
bits : 12 - 12 (1 bit)

WDU : Week day units
bits : 13 - 15 (3 bit)

YU : Year units in BCD format
bits : 16 - 19 (4 bit)

YT : Year tens in BCD format
bits : 20 - 23 (4 bit)


TAFCR

tamper and alternate function configuration register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAFCR TAFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMP1E TAMP1TRG TAMPIE TAMP2E TAMP2_TRG TAMPTS TAMPFREQ TAMPFLT TAMP_PRCH TAMP_PUDIS PC13VALUE PC13MODE PC14VALUE PC14MODE PC15VALUE PC15MODE

TAMP1E : RTC_TAMP1 input detection enable
bits : 0 - 0 (1 bit)

TAMP1TRG : Active level for RTC_TAMP1 input
bits : 1 - 1 (1 bit)

TAMPIE : Tamper interrupt enable
bits : 2 - 2 (1 bit)

TAMP2E : RTC_TAMP2 input detection enable
bits : 3 - 3 (1 bit)

TAMP2_TRG : Active level for RTC_TAMP2 input
bits : 4 - 4 (1 bit)

TAMPTS : Activate timestamp on tamper detection event
bits : 7 - 7 (1 bit)

TAMPFREQ : Tamper sampling frequency
bits : 8 - 10 (3 bit)

TAMPFLT : RTC_TAMPx filter count
bits : 11 - 12 (2 bit)

TAMP_PRCH : RTC_TAMPx precharge duration
bits : 13 - 14 (2 bit)

TAMP_PUDIS : RTC_TAMPx pull-up disable
bits : 15 - 15 (1 bit)

PC13VALUE : RTC_ALARM output type/PC13 value
bits : 18 - 18 (1 bit)

PC13MODE : PC13 mode
bits : 19 - 19 (1 bit)

PC14VALUE : PC14 value
bits : 20 - 20 (1 bit)

PC14MODE : PC14 mode
bits : 21 - 21 (1 bit)

PC15VALUE : PC15 value
bits : 22 - 22 (1 bit)

PC15MODE : PC15 mode
bits : 23 - 23 (1 bit)


ALRMASSR

alarm A sub second register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALRMASSR ALRMASSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS MASKSS

SS : Sub seconds value
bits : 0 - 14 (15 bit)

MASKSS : Mask the most-significant bits starting at this bit
bits : 24 - 27 (4 bit)


BKP0R

backup register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP0R BKP0R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP

BKP : BKP
bits : 0 - 31 (32 bit)


BKP1R

backup register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP1R BKP1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP

BKP : BKP
bits : 0 - 31 (32 bit)


BKP2R

backup register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP2R BKP2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP

BKP : BKP
bits : 0 - 31 (32 bit)


BKP3R

backup register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP3R BKP3R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP

BKP : BKP
bits : 0 - 31 (32 bit)


BKP4R

backup register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKP4R BKP4R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKP

BKP : BKP
bits : 0 - 31 (32 bit)


CR

control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSEDGE REFCKON BYPSHAD FMT ALRAE TSE ALRAIE TSIE ADD1H SUB1H BKP COSEL POL OSEL COE

TSEDGE : Time-stamp event active edge
bits : 3 - 3 (1 bit)
access : read-write

REFCKON : RTC_REFIN reference clock detection enable (50 or 60 Hz)
bits : 4 - 4 (1 bit)
access : read-write

BYPSHAD : Bypass the shadow registers
bits : 5 - 5 (1 bit)
access : read-write

FMT : Hour format
bits : 6 - 6 (1 bit)
access : read-write

ALRAE : Alarm A enable
bits : 8 - 8 (1 bit)
access : read-write

TSE : timestamp enable
bits : 11 - 11 (1 bit)
access : read-write

ALRAIE : Alarm A interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

TSIE : Time-stamp interrupt enable
bits : 15 - 15 (1 bit)
access : read-write

ADD1H : Add 1 hour (summer time change)
bits : 16 - 16 (1 bit)
access : write-only

SUB1H : Subtract 1 hour (winter time change)
bits : 17 - 17 (1 bit)
access : write-only

BKP : Backup
bits : 18 - 18 (1 bit)
access : read-write

COSEL : Calibration output selection
bits : 19 - 19 (1 bit)
access : read-write

POL : Output polarity
bits : 20 - 20 (1 bit)
access : read-write

OSEL : Output selection
bits : 21 - 22 (2 bit)
access : read-write

COE : Calibration output enable
bits : 23 - 23 (1 bit)
access : read-write


ISR

initialization and status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALRAWF SHPF INITS RSF INITF INIT ALRAF TSF TSOVF TAMP1F TAMP2F RECALPF

ALRAWF : Alarm A write flag
bits : 0 - 0 (1 bit)
access : read-only

SHPF : Shift operation pending
bits : 3 - 3 (1 bit)
access : read-write

INITS : Initialization status flag
bits : 4 - 4 (1 bit)
access : read-only

RSF : Registers synchronization flag
bits : 5 - 5 (1 bit)
access : read-write

INITF : Initialization flag
bits : 6 - 6 (1 bit)
access : read-only

INIT : Initialization mode
bits : 7 - 7 (1 bit)
access : read-write

ALRAF : Alarm A flag
bits : 8 - 8 (1 bit)
access : read-write

TSF : Time-stamp flag
bits : 11 - 11 (1 bit)
access : read-write

TSOVF : Time-stamp overflow flag
bits : 12 - 12 (1 bit)
access : read-write

TAMP1F : RTC_TAMP1 detection flag
bits : 13 - 13 (1 bit)
access : read-write

TAMP2F : RTC_TAMP2 detection flag
bits : 14 - 14 (1 bit)
access : read-write

RECALPF : Recalibration pending Flag
bits : 16 - 16 (1 bit)
access : read-only



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