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CEC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR

ISR

IER

CFGR

TXDR

RXDR


CR

control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CECEN TXSOM TXEOM

CECEN : CEC Enable
bits : 0 - 0 (1 bit)

TXSOM : Tx start of message
bits : 1 - 1 (1 bit)

TXEOM : Tx End Of Message
bits : 2 - 2 (1 bit)


ISR

Interrupt and Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBR RXEND RXOVR BRE SBPE LBPE RXACKE ARBLST TXBR TXEND TXUDR TXERR TXACKE

RXBR : Rx-Byte Received
bits : 0 - 0 (1 bit)

RXEND : End Of Reception
bits : 1 - 1 (1 bit)

RXOVR : Rx-Overrun
bits : 2 - 2 (1 bit)

BRE : Rx-Bit rising error
bits : 3 - 3 (1 bit)

SBPE : Rx-Short Bit period error
bits : 4 - 4 (1 bit)

LBPE : Rx-Long Bit Period Error
bits : 5 - 5 (1 bit)

RXACKE : Rx-Missing Acknowledge
bits : 6 - 6 (1 bit)

ARBLST : Arbitration Lost
bits : 7 - 7 (1 bit)

TXBR : Tx-Byte Request
bits : 8 - 8 (1 bit)

TXEND : End of Transmission
bits : 9 - 9 (1 bit)

TXUDR : Tx-Buffer Underrun
bits : 10 - 10 (1 bit)

TXERR : Tx-Error
bits : 11 - 11 (1 bit)

TXACKE : Tx-Missing acknowledge error
bits : 12 - 12 (1 bit)


IER

interrupt enable register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBRIE RXENDIE RXOVRIE BREIE SBPEIE LBPEIE RXACKIE ARBLSTIE TXBRIE TXENDIE TXUDRIE TXERRIE TXACKIE

RXBRIE : Rx-Byte Received Interrupt Enable
bits : 0 - 0 (1 bit)

RXENDIE : End Of Reception Interrupt Enable
bits : 1 - 1 (1 bit)

RXOVRIE : Rx-Buffer Overrun Interrupt Enable
bits : 2 - 2 (1 bit)

BREIE : Bit Rising Error Interrupt Enable
bits : 3 - 3 (1 bit)

SBPEIE : Short Bit Period Error Interrupt Enable
bits : 4 - 4 (1 bit)

LBPEIE : Long Bit Period Error Interrupt Enable
bits : 5 - 5 (1 bit)

RXACKIE : Rx-Missing Acknowledge Error Interrupt Enable
bits : 6 - 6 (1 bit)

ARBLSTIE : Arbitration Lost Interrupt Enable
bits : 7 - 7 (1 bit)

TXBRIE : Tx-Byte Request Interrupt Enable
bits : 8 - 8 (1 bit)

TXENDIE : Tx-End of message interrupt enable
bits : 9 - 9 (1 bit)

TXUDRIE : Tx-Underrun interrupt enable
bits : 10 - 10 (1 bit)

TXERRIE : Tx-Error Interrupt Enable
bits : 11 - 11 (1 bit)

TXACKIE : Tx-Missing Acknowledge Error Interrupt Enable
bits : 12 - 12 (1 bit)


CFGR

configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OAR LSTN SFT RXTOL BRESTP BREGEN LBPEGEN

OAR : Own Address
bits : 0 - 3 (4 bit)

LSTN : Listen mode
bits : 4 - 4 (1 bit)

SFT : Signal Free Time
bits : 5 - 7 (3 bit)

RXTOL : Rx-Tolerance
bits : 8 - 8 (1 bit)

BRESTP : Rx-stop on bit rising error
bits : 9 - 9 (1 bit)

BREGEN : Generate error-bit on bit rising error
bits : 10 - 10 (1 bit)

LBPEGEN : Generate Error-Bit on Long Bit Period Error
bits : 11 - 11 (1 bit)


TXDR

Tx data register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDR TXDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXD

TXD : Tx Data register
bits : 0 - 7 (8 bit)


RXDR

Rx Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDR RXDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDR

RXDR : CEC Rx Data Register
bits : 0 - 7 (8 bit)



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