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CRS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR

CFGR

ISR

ICR


CR

control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCOKIE SYNCWARNIE ERRIE ESYNCIE CEN AUTOTRIMEN SWSYNC TRIM

SYNCOKIE : SYNC event OK interrupt enable
bits : 0 - 0 (1 bit)

SYNCWARNIE : SYNC warning interrupt enable
bits : 1 - 1 (1 bit)

ERRIE : Synchronization or trimming error interrupt enable
bits : 2 - 2 (1 bit)

ESYNCIE : Expected SYNC interrupt enable
bits : 3 - 3 (1 bit)

CEN : Frequency error counter enable
bits : 5 - 5 (1 bit)

AUTOTRIMEN : Automatic trimming enable
bits : 6 - 6 (1 bit)

SWSYNC : Generate software SYNC event
bits : 7 - 7 (1 bit)

TRIM : HSI48 oscillator smooth trimming
bits : 8 - 13 (6 bit)


CFGR

configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELOAD FELIM SYNCDIV SYNCSRC SYNCPOL

RELOAD : Counter reload value
bits : 0 - 15 (16 bit)

FELIM : Frequency error limit
bits : 16 - 23 (8 bit)

SYNCDIV : SYNC divider
bits : 24 - 26 (3 bit)

SYNCSRC : SYNC signal source selection
bits : 28 - 29 (2 bit)

SYNCPOL : SYNC polarity selection
bits : 31 - 31 (1 bit)


ISR

interrupt and status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCOKF SYNCWARNF ERRF ESYNCF SYNCERR SYNCMISS TRIMOVF FEDIR FECAP

SYNCOKF : SYNC event OK flag
bits : 0 - 0 (1 bit)

SYNCWARNF : SYNC warning flag
bits : 1 - 1 (1 bit)

ERRF : Error flag
bits : 2 - 2 (1 bit)

ESYNCF : Expected SYNC flag
bits : 3 - 3 (1 bit)

SYNCERR : SYNC error
bits : 8 - 8 (1 bit)

SYNCMISS : SYNC missed
bits : 9 - 9 (1 bit)

TRIMOVF : Trimming overflow or underflow
bits : 10 - 10 (1 bit)

FEDIR : Frequency error direction
bits : 15 - 15 (1 bit)

FECAP : Frequency error capture
bits : 16 - 31 (16 bit)


ICR

interrupt flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICR ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCOKC SYNCWARNC ERRC ESYNCC

SYNCOKC : SYNC event OK clear flag
bits : 0 - 0 (1 bit)

SYNCWARNC : SYNC warning clear flag
bits : 1 - 1 (1 bit)

ERRC : Error clear flag
bits : 2 - 2 (1 bit)

ESYNCC : Expected SYNC clear flag
bits : 3 - 3 (1 bit)



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