\n

RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x7C byte (0x0)
mem_usage : registers
protection :

Registers

LKPCR

RCHFCR

RCHFTR

PLLCR

LPOSCCR

LPOSCTR

XTLFCR

PCLKCR1

PCLKCR2

PCLKCR3

PCLKCR4

LSCLKSEL

SOFTRST

AHBMCR

PRSTEN

AHBRSTCR

APBRSTCR1

APBRSTCR2

XTHFCR

RCMFCR

RCMFTR

OPCCR1

OPCCR2

PHYCR

PHYBCKCR

RSTFR

SYSCLKCR


LKPCR

Lockup reset Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LKPCR LKPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LKUPRST_EN

LKUPRST_EN : LKUPRST_EN field description
bits : 1 - 1 (1 bit)


RCHFCR

RCHF Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCHFCR RCHFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN FSEL

EN : EN field description
bits : 0 - 0 (1 bit)

FSEL : FSEL field description
bits : 16 - 19 (4 bit)


RCHFTR

RCHF Trim Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCHFTR RCHFTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM

TRIM : TRIM field description
bits : 0 - 6 (7 bit)


PLLCR

PLL Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCR PLLCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN INSEL OSEL REFPRSC LOCKED DB

EN : EN field description
bits : 0 - 0 (1 bit)
access : read-write

INSEL : INSEL field description
bits : 1 - 1 (1 bit)
access : read-write

OSEL : OSEL field description
bits : 3 - 3 (1 bit)
access : read-write

REFPRSC : REFPRSC field description
bits : 4 - 6 (3 bit)
access : read-write

LOCKED : LOCKED field description
bits : 7 - 7 (1 bit)
access : read-only

DB : DB field description
bits : 16 - 22 (7 bit)
access : read-write


LPOSCCR

LPOSC Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPOSCCR LPOSCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPM_LPO_OFF LPO_ENB LPO_CHOP_EN

LPM_LPO_OFF : LPM_LPO_OFF field description
bits : 0 - 0 (1 bit)
access : read-write

LPO_ENB : LPO_ENB field description
bits : 1 - 1 (1 bit)
access : read-only

LPO_CHOP_EN : LPO_CHOP_EN field description
bits : 2 - 2 (1 bit)
access : read-write


LPOSCTR

LPOSC Trim Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPOSCTR LPOSCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPOTRIM

LPOTRIM : LPOTRIM field description
bits : 0 - 7 (8 bit)


XTLFCR

XTLF Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTLFCR XTLFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPW EN

IPW : IPW field description
bits : 0 - 2 (3 bit)

EN : EN field description
bits : 8 - 11 (4 bit)


PCLKCR1

Peripheral bus Clock Control Register1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLKCR1 PCLKCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPT_PCE USB_PCE RTC_PCE PMU_PCE SCU_PCE IWDT_PCE ANAC_PCE PAD_PCE DCU_PCE

LPT_PCE : LPT_PCE field description
bits : 0 - 0 (1 bit)

USB_PCE : USB_PCE field description
bits : 1 - 1 (1 bit)

RTC_PCE : RTC_PCE field description
bits : 2 - 2 (1 bit)

PMU_PCE : PMU_PCE field description
bits : 3 - 3 (1 bit)

SCU_PCE : SCU_PCE field description
bits : 4 - 4 (1 bit)

IWDT_PCE : IWDT_PCE field description
bits : 5 - 5 (1 bit)

ANAC_PCE : ANAC_PCE field description
bits : 6 - 6 (1 bit)

PAD_PCE : PAD_PCE field description
bits : 7 - 7 (1 bit)

DCU_PCE : DCU_PCE field description
bits : 31 - 31 (1 bit)


PCLKCR2

Peripheral bus Clock Control Register2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLKCR2 PCLKCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC_PCE RNG_PCE AES_PCE LCD_PCE DMA_PCE FLASH_PCE RAMBIST_PCE WWDT_PCE ADC_PCE HDIV_PCE

CRC_PCE : CRC_PCE field description
bits : 0 - 0 (1 bit)

RNG_PCE : RNG_PCE field description
bits : 1 - 1 (1 bit)

AES_PCE : AES_PCE field description
bits : 2 - 2 (1 bit)

LCD_PCE : LCD_PCE field description
bits : 3 - 3 (1 bit)

DMA_PCE : DMA_PCE field description
bits : 4 - 4 (1 bit)

FLASH_PCE : FLASH_PCE field description
bits : 5 - 5 (1 bit)

RAMBIST_PCE : RAMBIST_PCE field description
bits : 6 - 6 (1 bit)

WWDT_PCE : WWDT_PCE field description
bits : 7 - 7 (1 bit)

ADC_PCE : ADC_PCE field description
bits : 8 - 8 (1 bit)

HDIV_PCE : HDIV_PCE field description
bits : 9 - 9 (1 bit)


PCLKCR3

Peripheral bus Clock Control Register3
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLKCR3 PCLKCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI1_PCE SPI2_PCE UART0_PCE UART1_PCE UART4_PCE UART5_PCE UCIR_PCE LPUART0_PCE U7816_PCE LPUART1_PCE I2C_PCE

SPI1_PCE : SPI1_PCE field description
bits : 0 - 0 (1 bit)

SPI2_PCE : SPI2_PCE field description
bits : 1 - 1 (1 bit)

UART0_PCE : UART0_PCE field description
bits : 8 - 8 (1 bit)

UART1_PCE : UART1_PCE field description
bits : 9 - 9 (1 bit)

UART4_PCE : UART4_PCE field description
bits : 12 - 12 (1 bit)

UART5_PCE : UART5_PCE field description
bits : 13 - 13 (1 bit)

UCIR_PCE : UCIR_PCE field description
bits : 14 - 14 (1 bit)

LPUART0_PCE : LPUART0_PCE field description
bits : 15 - 15 (1 bit)

U7816_PCE : U7816_PCE field description
bits : 16 - 16 (1 bit)

LPUART1_PCE : LPUART1_PCE field description
bits : 18 - 18 (1 bit)

I2C_PCE : I2C_PCE field description
bits : 24 - 24 (1 bit)


PCLKCR4

Peripheral bus Clock Control Register4
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCLKCR4 PCLKCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BT_PCE GT0_PCE GT1_PCE AT_PCE

BT_PCE : BT_PCE field description
bits : 0 - 0 (1 bit)

GT0_PCE : GT0_PCE field description
bits : 2 - 2 (1 bit)

GT1_PCE : GT1_PCE field description
bits : 3 - 3 (1 bit)

AT_PCE : AT_PCE field description
bits : 4 - 4 (1 bit)


LSCLKSEL

LSCLK Select Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LSCLKSEL LSCLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : SEL field description
bits : 0 - 7 (8 bit)


SOFTRST

Software Reset Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SOFTRST SOFTRST write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOFTRST

SOFTRST : SOFTRST field description
bits : 0 - 31 (32 bit)


AHBMCR

AHB Master Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBMCR AHBMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPRIL

MPRIL : MPRIL field description
bits : 0 - 0 (1 bit)


PRSTEN

Peripheral Reset Enable Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PRSTEN PRSTEN write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERHRSTEN

PERHRSTEN : PERHRSTEN field description
bits : 0 - 31 (32 bit)


AHBRSTCR

AHB Peripherals Reset Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBRSTCR AHBRSTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMARST USBRST

DMARST : DMARST field description
bits : 0 - 0 (1 bit)

USBRST : USBRST field description
bits : 1 - 1 (1 bit)


APBRSTCR1

APB Peripherals Reset Control Register1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBRSTCR1 APBRSTCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPT32RST I2C1RST LPUART0RST SPI2RST U7816RST LCDRST GPT0RST GPT1RST UART4RST UART5RST

LPT32RST : LPT32RST field description
bits : 0 - 0 (1 bit)

I2C1RST : I2C1RST field description
bits : 3 - 3 (1 bit)

LPUART0RST : LPUART0RST field description
bits : 6 - 6 (1 bit)

SPI2RST : SPI2RST field description
bits : 10 - 10 (1 bit)

U7816RST : U7816RST field description
bits : 14 - 14 (1 bit)

LCDRST : LCDRST field description
bits : 16 - 16 (1 bit)

GPT0RST : GPT0RST field description
bits : 24 - 24 (1 bit)

GPT1RST : GPT1RST field description
bits : 25 - 25 (1 bit)

UART4RST : UART4RST field description
bits : 30 - 30 (1 bit)

UART5RST : UART5RST field description
bits : 31 - 31 (1 bit)


APBRSTCR2

APB Peripherals Reset Control Register2
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBRSTCR2 APBRSTCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPUART1RST UCIRRST SPI1RST UART0RST UART1RST RNGRST CRCRST AESRST HDVRST OPARST ADCRST ADCCRST BT32RST ATRST

LPUART1RST : LPUART1RST field description
bits : 7 - 7 (1 bit)

UCIRRST : UCIRRST field description
bits : 8 - 8 (1 bit)

SPI1RST : SPI1RST field description
bits : 9 - 9 (1 bit)

UART0RST : UART0RST field description
bits : 11 - 11 (1 bit)

UART1RST : UART1RST field description
bits : 12 - 12 (1 bit)

RNGRST : RNGRST field description
bits : 16 - 16 (1 bit)

CRCRST : CRCRST field description
bits : 17 - 17 (1 bit)

AESRST : AESRST field description
bits : 18 - 18 (1 bit)

HDVRST : HDVRST field description
bits : 19 - 19 (1 bit)

OPARST : OPARST field description
bits : 22 - 22 (1 bit)

ADCRST : ADCRST field description
bits : 23 - 23 (1 bit)

ADCCRST : ADCCRST field description
bits : 24 - 24 (1 bit)

BT32RST : BT32RST field description
bits : 28 - 28 (1 bit)

ATRST : ATRST field description
bits : 31 - 31 (1 bit)


XTHFCR

XTHF Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTHFCR XTHFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN CFG

EN : EN field description
bits : 0 - 0 (1 bit)

CFG : CFG field description
bits : 8 - 10 (3 bit)


RCMFCR

RCMF Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCMFCR RCMFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PSC

EN : EN field description
bits : 0 - 0 (1 bit)

PSC : PSC field description
bits : 16 - 17 (2 bit)


RCMFTR

RCMF Trim Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCMFTR RCMFTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM

TRIM : TRIM field description
bits : 0 - 6 (7 bit)


OPCCR1

Peripheral Operation Clock Control Register1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPCCR1 OPCCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART0CKS UART1CKS ATCKS UART0CKE UART1CKE ATCKE I2CCKS I2CCKE LPUART0CKS LPUART1CKS LPUART0CKE LPUART1CKE EXTICKS EXTICKE

UART0CKS : UART0CKS field description
bits : 0 - 1 (2 bit)

UART1CKS : UART1CKS field description
bits : 2 - 3 (2 bit)

ATCKS : ATCKS field description
bits : 6 - 7 (2 bit)

UART0CKE : UART0CKE field description
bits : 8 - 8 (1 bit)

UART1CKE : UART1CKE field description
bits : 9 - 9 (1 bit)

ATCKE : ATCKE field description
bits : 15 - 15 (1 bit)

I2CCKS : I2CCKS field description
bits : 16 - 17 (2 bit)

I2CCKE : I2CCKE field description
bits : 20 - 20 (1 bit)

LPUART0CKS : LPUART0CKS field description
bits : 24 - 25 (2 bit)

LPUART1CKS : LPUART1CKS field description
bits : 26 - 27 (2 bit)

LPUART0CKE : LPUART0CKE field description
bits : 28 - 28 (1 bit)

LPUART1CKE : LPUART1CKE field description
bits : 29 - 29 (1 bit)

EXTICKS : EXTICKS field description
bits : 30 - 30 (1 bit)

EXTICKE : EXTICKE field description
bits : 31 - 31 (1 bit)


OPCCR2

Peripheral Operation Clock Control Register2
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPCCR2 OPCCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BTCKS BTCKE LPTCKS LPTCKE ADCCKS USBREFCKS ADCCKE RNGCKE FLASHCKE USBREFCKE ADCPRSC RNGPRSC

BTCKS : BTCKS field description
bits : 0 - 1 (2 bit)

BTCKE : BTCKE field description
bits : 4 - 4 (1 bit)

LPTCKS : LPTCKS field description
bits : 8 - 9 (2 bit)

LPTCKE : LPTCKE field description
bits : 12 - 12 (1 bit)

ADCCKS : ADCCKS field description
bits : 16 - 17 (2 bit)

USBREFCKS : USBREFCKS field description
bits : 18 - 19 (2 bit)

ADCCKE : ADCCKE field description
bits : 20 - 20 (1 bit)

RNGCKE : RNGCKE field description
bits : 21 - 21 (1 bit)

FLASHCKE : FLASHCKE field description
bits : 22 - 22 (1 bit)

USBREFCKE : USBREFCKE field description
bits : 23 - 23 (1 bit)

ADCPRSC : ADCPRSC field description
bits : 24 - 26 (3 bit)

RNGPRSC : RNGPRSC field description
bits : 28 - 30 (3 bit)


PHYCR

PHY Control Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHYCR PHYCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NONCRY_RSTB BCKPD PLVREADY_33V PD PHY_PONRST_B

NONCRY_RSTB : NONCRY_RSTB field description
bits : 0 - 0 (1 bit)

BCKPD : BCKPD field description
bits : 1 - 1 (1 bit)

PLVREADY_33V : PLVREADY_33V field description
bits : 2 - 2 (1 bit)

PD : PD field description
bits : 3 - 3 (1 bit)

PHY_PONRST_B : PHY_PONRST_B field description
bits : 4 - 4 (1 bit)


PHYBCKCR

PHY BCK Control Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHYBCKCR PHYBCKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTCLKSEL CLK_RDY CK48M_EN

OUTCLKSEL : OUTCLKSEL field description
bits : 0 - 0 (1 bit)
access : read-write

CLK_RDY : CLK_RDY field description
bits : 7 - 7 (1 bit)
access : read-only

CK48M_EN : CK48M_EN field description
bits : 8 - 8 (1 bit)
access : read-write


RSTFR

Reset Flag Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTFR RSTFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVICN_FLAG LKUPN_FLAG WWDTN_FLAG IWDTN_FLAG SOFTN_FLAG PDRN_FLAG PORN_FLAG TESTN_FLAG NRSTN_FLAG MDFN_FLAG

NVICN_FLAG : NVICN_FLAG field description
bits : 0 - 0 (1 bit)

LKUPN_FLAG : LKUPN_FLAG field description
bits : 1 - 1 (1 bit)

WWDTN_FLAG : WWDTN_FLAG field description
bits : 2 - 2 (1 bit)

IWDTN_FLAG : IWDTN_FLAG field description
bits : 4 - 4 (1 bit)

SOFTN_FLAG : SOFTN_FLAG field description
bits : 5 - 5 (1 bit)

PDRN_FLAG : PDRN_FLAG field description
bits : 8 - 8 (1 bit)

PORN_FLAG : PORN_FLAG field description
bits : 9 - 9 (1 bit)

TESTN_FLAG : TESTN_FLAG field description
bits : 10 - 10 (1 bit)

NRSTN_FLAG : NRSTN_FLAG field description
bits : 11 - 11 (1 bit)

MDFN_FLAG : MDFN_FLAG field description
bits : 12 - 12 (1 bit)


SYSCLKCR

System Clock Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCLKCR SYSCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSCLKSEL BCKOSEL AHBPRES APBPRES1 APBPRES2 SLP_ENEXTI LSCATS

SYSCLKSEL : SYSCLKSEL field description
bits : 0 - 2 (3 bit)

BCKOSEL : BCKOSEL field description
bits : 3 - 3 (1 bit)

AHBPRES : AHBPRES field description
bits : 8 - 10 (3 bit)

APBPRES1 : APBPRES1 field description
bits : 16 - 18 (3 bit)

APBPRES2 : APBPRES2 field description
bits : 19 - 21 (3 bit)

SLP_ENEXTI : SLP_ENEXTI field description
bits : 25 - 25 (1 bit)

LSCATS : LSCATS field description
bits : 27 - 27 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.