\n
address_offset : 0x0 Bytes (0x0)
size : 0x7C byte (0x0)
mem_usage : registers
protection :
Lockup reset Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LKUPRST_EN : LKUPRST_EN field description
bits : 1 - 1 (1 bit)
RCHF Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
FSEL : FSEL field description
bits : 16 - 19 (4 bit)
RCHF Trim Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : TRIM field description
bits : 0 - 6 (7 bit)
PLL Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
access : read-write
INSEL : INSEL field description
bits : 1 - 1 (1 bit)
access : read-write
OSEL : OSEL field description
bits : 3 - 3 (1 bit)
access : read-write
REFPRSC : REFPRSC field description
bits : 4 - 6 (3 bit)
access : read-write
LOCKED : LOCKED field description
bits : 7 - 7 (1 bit)
access : read-only
DB : DB field description
bits : 16 - 22 (7 bit)
access : read-write
LPOSC Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPM_LPO_OFF : LPM_LPO_OFF field description
bits : 0 - 0 (1 bit)
access : read-write
LPO_ENB : LPO_ENB field description
bits : 1 - 1 (1 bit)
access : read-only
LPO_CHOP_EN : LPO_CHOP_EN field description
bits : 2 - 2 (1 bit)
access : read-write
LPOSC Trim Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPOTRIM : LPOTRIM field description
bits : 0 - 7 (8 bit)
XTLF Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPW : IPW field description
bits : 0 - 2 (3 bit)
EN : EN field description
bits : 8 - 11 (4 bit)
Peripheral bus Clock Control Register1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPT_PCE : LPT_PCE field description
bits : 0 - 0 (1 bit)
USB_PCE : USB_PCE field description
bits : 1 - 1 (1 bit)
RTC_PCE : RTC_PCE field description
bits : 2 - 2 (1 bit)
PMU_PCE : PMU_PCE field description
bits : 3 - 3 (1 bit)
SCU_PCE : SCU_PCE field description
bits : 4 - 4 (1 bit)
IWDT_PCE : IWDT_PCE field description
bits : 5 - 5 (1 bit)
ANAC_PCE : ANAC_PCE field description
bits : 6 - 6 (1 bit)
PAD_PCE : PAD_PCE field description
bits : 7 - 7 (1 bit)
DCU_PCE : DCU_PCE field description
bits : 31 - 31 (1 bit)
Peripheral bus Clock Control Register2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_PCE : CRC_PCE field description
bits : 0 - 0 (1 bit)
RNG_PCE : RNG_PCE field description
bits : 1 - 1 (1 bit)
AES_PCE : AES_PCE field description
bits : 2 - 2 (1 bit)
LCD_PCE : LCD_PCE field description
bits : 3 - 3 (1 bit)
DMA_PCE : DMA_PCE field description
bits : 4 - 4 (1 bit)
FLASH_PCE : FLASH_PCE field description
bits : 5 - 5 (1 bit)
RAMBIST_PCE : RAMBIST_PCE field description
bits : 6 - 6 (1 bit)
WWDT_PCE : WWDT_PCE field description
bits : 7 - 7 (1 bit)
ADC_PCE : ADC_PCE field description
bits : 8 - 8 (1 bit)
HDIV_PCE : HDIV_PCE field description
bits : 9 - 9 (1 bit)
Peripheral bus Clock Control Register3
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI1_PCE : SPI1_PCE field description
bits : 0 - 0 (1 bit)
SPI2_PCE : SPI2_PCE field description
bits : 1 - 1 (1 bit)
UART0_PCE : UART0_PCE field description
bits : 8 - 8 (1 bit)
UART1_PCE : UART1_PCE field description
bits : 9 - 9 (1 bit)
UART4_PCE : UART4_PCE field description
bits : 12 - 12 (1 bit)
UART5_PCE : UART5_PCE field description
bits : 13 - 13 (1 bit)
UCIR_PCE : UCIR_PCE field description
bits : 14 - 14 (1 bit)
LPUART0_PCE : LPUART0_PCE field description
bits : 15 - 15 (1 bit)
U7816_PCE : U7816_PCE field description
bits : 16 - 16 (1 bit)
LPUART1_PCE : LPUART1_PCE field description
bits : 18 - 18 (1 bit)
I2C_PCE : I2C_PCE field description
bits : 24 - 24 (1 bit)
Peripheral bus Clock Control Register4
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BT_PCE : BT_PCE field description
bits : 0 - 0 (1 bit)
GT0_PCE : GT0_PCE field description
bits : 2 - 2 (1 bit)
GT1_PCE : GT1_PCE field description
bits : 3 - 3 (1 bit)
AT_PCE : AT_PCE field description
bits : 4 - 4 (1 bit)
LSCLK Select Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : SEL field description
bits : 0 - 7 (8 bit)
Software Reset Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SOFTRST : SOFTRST field description
bits : 0 - 31 (32 bit)
AHB Master Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPRIL : MPRIL field description
bits : 0 - 0 (1 bit)
Peripheral Reset Enable Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PERHRSTEN : PERHRSTEN field description
bits : 0 - 31 (32 bit)
AHB Peripherals Reset Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMARST : DMARST field description
bits : 0 - 0 (1 bit)
USBRST : USBRST field description
bits : 1 - 1 (1 bit)
APB Peripherals Reset Control Register1
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPT32RST : LPT32RST field description
bits : 0 - 0 (1 bit)
I2C1RST : I2C1RST field description
bits : 3 - 3 (1 bit)
LPUART0RST : LPUART0RST field description
bits : 6 - 6 (1 bit)
SPI2RST : SPI2RST field description
bits : 10 - 10 (1 bit)
U7816RST : U7816RST field description
bits : 14 - 14 (1 bit)
LCDRST : LCDRST field description
bits : 16 - 16 (1 bit)
GPT0RST : GPT0RST field description
bits : 24 - 24 (1 bit)
GPT1RST : GPT1RST field description
bits : 25 - 25 (1 bit)
UART4RST : UART4RST field description
bits : 30 - 30 (1 bit)
UART5RST : UART5RST field description
bits : 31 - 31 (1 bit)
APB Peripherals Reset Control Register2
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPUART1RST : LPUART1RST field description
bits : 7 - 7 (1 bit)
UCIRRST : UCIRRST field description
bits : 8 - 8 (1 bit)
SPI1RST : SPI1RST field description
bits : 9 - 9 (1 bit)
UART0RST : UART0RST field description
bits : 11 - 11 (1 bit)
UART1RST : UART1RST field description
bits : 12 - 12 (1 bit)
RNGRST : RNGRST field description
bits : 16 - 16 (1 bit)
CRCRST : CRCRST field description
bits : 17 - 17 (1 bit)
AESRST : AESRST field description
bits : 18 - 18 (1 bit)
HDVRST : HDVRST field description
bits : 19 - 19 (1 bit)
OPARST : OPARST field description
bits : 22 - 22 (1 bit)
ADCRST : ADCRST field description
bits : 23 - 23 (1 bit)
ADCCRST : ADCCRST field description
bits : 24 - 24 (1 bit)
BT32RST : BT32RST field description
bits : 28 - 28 (1 bit)
ATRST : ATRST field description
bits : 31 - 31 (1 bit)
XTHF Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
CFG : CFG field description
bits : 8 - 10 (3 bit)
RCMF Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
PSC : PSC field description
bits : 16 - 17 (2 bit)
RCMF Trim Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : TRIM field description
bits : 0 - 6 (7 bit)
Peripheral Operation Clock Control Register1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART0CKS : UART0CKS field description
bits : 0 - 1 (2 bit)
UART1CKS : UART1CKS field description
bits : 2 - 3 (2 bit)
ATCKS : ATCKS field description
bits : 6 - 7 (2 bit)
UART0CKE : UART0CKE field description
bits : 8 - 8 (1 bit)
UART1CKE : UART1CKE field description
bits : 9 - 9 (1 bit)
ATCKE : ATCKE field description
bits : 15 - 15 (1 bit)
I2CCKS : I2CCKS field description
bits : 16 - 17 (2 bit)
I2CCKE : I2CCKE field description
bits : 20 - 20 (1 bit)
LPUART0CKS : LPUART0CKS field description
bits : 24 - 25 (2 bit)
LPUART1CKS : LPUART1CKS field description
bits : 26 - 27 (2 bit)
LPUART0CKE : LPUART0CKE field description
bits : 28 - 28 (1 bit)
LPUART1CKE : LPUART1CKE field description
bits : 29 - 29 (1 bit)
EXTICKS : EXTICKS field description
bits : 30 - 30 (1 bit)
EXTICKE : EXTICKE field description
bits : 31 - 31 (1 bit)
Peripheral Operation Clock Control Register2
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTCKS : BTCKS field description
bits : 0 - 1 (2 bit)
BTCKE : BTCKE field description
bits : 4 - 4 (1 bit)
LPTCKS : LPTCKS field description
bits : 8 - 9 (2 bit)
LPTCKE : LPTCKE field description
bits : 12 - 12 (1 bit)
ADCCKS : ADCCKS field description
bits : 16 - 17 (2 bit)
USBREFCKS : USBREFCKS field description
bits : 18 - 19 (2 bit)
ADCCKE : ADCCKE field description
bits : 20 - 20 (1 bit)
RNGCKE : RNGCKE field description
bits : 21 - 21 (1 bit)
FLASHCKE : FLASHCKE field description
bits : 22 - 22 (1 bit)
USBREFCKE : USBREFCKE field description
bits : 23 - 23 (1 bit)
ADCPRSC : ADCPRSC field description
bits : 24 - 26 (3 bit)
RNGPRSC : RNGPRSC field description
bits : 28 - 30 (3 bit)
PHY Control Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONCRY_RSTB : NONCRY_RSTB field description
bits : 0 - 0 (1 bit)
BCKPD : BCKPD field description
bits : 1 - 1 (1 bit)
PLVREADY_33V : PLVREADY_33V field description
bits : 2 - 2 (1 bit)
PD : PD field description
bits : 3 - 3 (1 bit)
PHY_PONRST_B : PHY_PONRST_B field description
bits : 4 - 4 (1 bit)
PHY BCK Control Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTCLKSEL : OUTCLKSEL field description
bits : 0 - 0 (1 bit)
access : read-write
CLK_RDY : CLK_RDY field description
bits : 7 - 7 (1 bit)
access : read-only
CK48M_EN : CK48M_EN field description
bits : 8 - 8 (1 bit)
access : read-write
Reset Flag Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVICN_FLAG : NVICN_FLAG field description
bits : 0 - 0 (1 bit)
LKUPN_FLAG : LKUPN_FLAG field description
bits : 1 - 1 (1 bit)
WWDTN_FLAG : WWDTN_FLAG field description
bits : 2 - 2 (1 bit)
IWDTN_FLAG : IWDTN_FLAG field description
bits : 4 - 4 (1 bit)
SOFTN_FLAG : SOFTN_FLAG field description
bits : 5 - 5 (1 bit)
PDRN_FLAG : PDRN_FLAG field description
bits : 8 - 8 (1 bit)
PORN_FLAG : PORN_FLAG field description
bits : 9 - 9 (1 bit)
TESTN_FLAG : TESTN_FLAG field description
bits : 10 - 10 (1 bit)
NRSTN_FLAG : NRSTN_FLAG field description
bits : 11 - 11 (1 bit)
MDFN_FLAG : MDFN_FLAG field description
bits : 12 - 12 (1 bit)
System Clock Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCLKSEL : SYSCLKSEL field description
bits : 0 - 2 (3 bit)
BCKOSEL : BCKOSEL field description
bits : 3 - 3 (1 bit)
AHBPRES : AHBPRES field description
bits : 8 - 10 (3 bit)
APBPRES1 : APBPRES1 field description
bits : 16 - 18 (3 bit)
APBPRES2 : APBPRES2 field description
bits : 19 - 21 (3 bit)
SLP_ENEXTI : SLP_ENEXTI field description
bits : 25 - 25 (1 bit)
LSCATS : LSCATS field description
bits : 27 - 27 (1 bit)
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