\n
address_offset : 0x0 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection :
AES Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
DATATYP : DATATYP field description
bits : 1 - 2 (2 bit)
MODE : MODE field description
bits : 3 - 4 (2 bit)
CHMOD : CHMOD field description
bits : 5 - 6 (2 bit)
DMAIEN : DMAIEN field description
bits : 11 - 11 (1 bit)
DMAOEN : DMAOEN field description
bits : 12 - 12 (1 bit)
KEYLEN : KEYLEN field description
bits : 13 - 14 (2 bit)
AES Data Output Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DOUT : DOUT field description
bits : 0 - 31 (32 bit)
AES Key Register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYx : KEYx field description
bits : 0 - 31 (32 bit)
AES Key Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYx : KEYx field description
bits : 0 - 31 (32 bit)
AES Key Register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYx : KEYx field description
bits : 0 - 31 (32 bit)
AES Key Register 3
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYx : KEYx field description
bits : 0 - 31 (32 bit)
AES Key Register 4
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYx : KEYx field description
bits : 0 - 31 (32 bit)
AES Key Register 5
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYx : KEYx field description
bits : 0 - 31 (32 bit)
AES Key Register 6
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYx : KEYx field description
bits : 0 - 31 (32 bit)
AES Key Register 7
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYx : KEYx field description
bits : 0 - 31 (32 bit)
AES Initial Vector Register 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVRx : IVRx field description
bits : 0 - 31 (32 bit)
AES Initial Vector Register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVRx : IVRx field description
bits : 0 - 31 (32 bit)
AES Initial Vector Register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVRx : IVRx field description
bits : 0 - 31 (32 bit)
AES Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCF_IE : CCF_IE field description
bits : 0 - 0 (1 bit)
RDERR_IE : RDERR_IE field description
bits : 1 - 1 (1 bit)
WRERR_IE : WRERR_IE field description
bits : 2 - 2 (1 bit)
AES Initial Vector Register 3
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVRx : IVRx field description
bits : 0 - 31 (32 bit)
AES Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCF : CCF field description
bits : 0 - 0 (1 bit)
RDERR : RDERR field description
bits : 1 - 1 (1 bit)
WRERR : WRERR field description
bits : 2 - 2 (1 bit)
AES Data Input Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIN : DIN field description
bits : 0 - 31 (32 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.