\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
SPI1 Control Register1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPHA : CPHA field description
bits : 0 - 0 (1 bit)
CPOL : CPOL field description
bits : 1 - 1 (1 bit)
LSBF : LSBF field description
bits : 2 - 2 (1 bit)
BAUD : BAUD field description
bits : 3 - 5 (3 bit)
WAIT : WAIT field description
bits : 6 - 7 (2 bit)
MM : MM field description
bits : 8 - 8 (1 bit)
SSPA : SSPA field description
bits : 9 - 9 (1 bit)
MSPA : MSPA field description
bits : 10 - 10 (1 bit)
IOSWAP : IOSWAP field description
bits : 11 - 11 (1 bit)
SPI1 Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBF : RXBF field description
bits : 0 - 0 (1 bit)
access : read-only
TXBE : TXBE field description
bits : 1 - 1 (1 bit)
access : read-only
SERR : SERR field description
bits : 5 - 5 (1 bit)
access : read-only
MERR : MERR field description
bits : 6 - 6 (1 bit)
access : read-only
BUSY : BUSY field description
bits : 8 - 8 (1 bit)
access : read-only
TXCOL : TXCOL field description
bits : 9 - 9 (1 bit)
access : read-write
RXCOL : RXCOL field description
bits : 10 - 10 (1 bit)
access : read-write
DCN_TX : DCN_TX field description
bits : 12 - 12 (1 bit)
access : read-write
SPI1 Transmit Buffer
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXBUF : TXBUF field description
bits : 0 - 31 (32 bit)
SPI1 Receive Buffer
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXBUF : RXBUF field description
bits : 0 - 31 (32 bit)
SPI1 Control Register2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPIEN field description
bits : 0 - 0 (1 bit)
SSNSEN : SSNSEN field description
bits : 1 - 1 (1 bit)
SSN : SSN field description
bits : 2 - 2 (1 bit)
TXO : TXO field description
bits : 3 - 3 (1 bit)
TXO_AC : TXO_AC field description
bits : 4 - 4 (1 bit)
SSNM : SSNM field description
bits : 5 - 5 (1 bit)
CMD8b : CMD8b field description
bits : 6 - 6 (1 bit)
HD_RW : HD_RW field description
bits : 7 - 7 (1 bit)
HALFDUPLEX : HALFDUPLEX field description
bits : 8 - 8 (1 bit)
DLEN : DLEN field description
bits : 9 - 10 (2 bit)
RXO : RXO field description
bits : 11 - 11 (1 bit)
DUMMY_EN : DUMMY_EN field description
bits : 15 - 15 (1 bit)
SPI1 Control Register3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SERRC : SERRC field description
bits : 0 - 0 (1 bit)
MERRC : MERRC field description
bits : 1 - 1 (1 bit)
RXBFC : RXBFC field description
bits : 2 - 2 (1 bit)
TXBFC : TXBFC field description
bits : 3 - 3 (1 bit)
SPI1 Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIE : RXIE field description
bits : 0 - 0 (1 bit)
TXIE : TXIE field description
bits : 1 - 1 (1 bit)
ERRIE : ERRIE field description
bits : 2 - 2 (1 bit)
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