\n
address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection :
DMA Global Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
ADDRERR_EN : ADDRERR_EN field description
bits : 1 - 1 (1 bit)
Channel 1 Memory Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)
Channel 2 Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
HTIE : HTIE field description
bits : 1 - 1 (1 bit)
FTIE : FTIE field description
bits : 2 - 2 (1 bit)
CIRC : CIRC field description
bits : 3 - 3 (1 bit)
BDW : BDW field description
bits : 4 - 5 (2 bit)
DIR : DIR field description
bits : 6 - 6 (1 bit)
SSEL : SSEL field description
bits : 8 - 10 (3 bit)
INC : INC field description
bits : 11 - 11 (1 bit)
PRI : PRI field description
bits : 12 - 13 (2 bit)
TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)
Channel 2 Memory Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)
Channel 3 Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
HTIE : HTIE field description
bits : 1 - 1 (1 bit)
FTIE : FTIE field description
bits : 2 - 2 (1 bit)
CIRC : CIRC field description
bits : 3 - 3 (1 bit)
BDW : BDW field description
bits : 4 - 5 (2 bit)
DIR : DIR field description
bits : 6 - 6 (1 bit)
SSEL : SSEL field description
bits : 8 - 10 (3 bit)
INC : INC field description
bits : 11 - 11 (1 bit)
PRI : PRI field description
bits : 12 - 13 (2 bit)
TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)
Channel 3 Memory Address Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)
Channel 4 Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
HTIE : HTIE field description
bits : 1 - 1 (1 bit)
FTIE : FTIE field description
bits : 2 - 2 (1 bit)
CIRC : CIRC field description
bits : 3 - 3 (1 bit)
BDW : BDW field description
bits : 4 - 5 (2 bit)
DIR : DIR field description
bits : 6 - 6 (1 bit)
SSEL : SSEL field description
bits : 8 - 10 (3 bit)
INC : INC field description
bits : 11 - 11 (1 bit)
PRI : PRI field description
bits : 12 - 13 (2 bit)
TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)
Channel 4 Memory Address Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)
Channel 5 Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
HTIE : HTIE field description
bits : 1 - 1 (1 bit)
FTIE : FTIE field description
bits : 2 - 2 (1 bit)
CIRC : CIRC field description
bits : 3 - 3 (1 bit)
BDW : BDW field description
bits : 4 - 5 (2 bit)
DIR : DIR field description
bits : 6 - 6 (1 bit)
SSEL : SSEL field description
bits : 8 - 10 (3 bit)
INC : INC field description
bits : 11 - 11 (1 bit)
PRI : PRI field description
bits : 12 - 13 (2 bit)
TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)
Channel 5 Memory Address Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)
Channel 6 Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
HTIE : HTIE field description
bits : 1 - 1 (1 bit)
FTIE : FTIE field description
bits : 2 - 2 (1 bit)
CIRC : CIRC field description
bits : 3 - 3 (1 bit)
BDW : BDW field description
bits : 4 - 5 (2 bit)
DIR : DIR field description
bits : 6 - 6 (1 bit)
SSEL : SSEL field description
bits : 8 - 10 (3 bit)
INC : INC field description
bits : 11 - 11 (1 bit)
PRI : PRI field description
bits : 12 - 13 (2 bit)
TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)
Channel 6 Memory Address Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)
Channel 7 Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
HTIE : HTIE field description
bits : 1 - 1 (1 bit)
FTIE : FTIE field description
bits : 2 - 2 (1 bit)
FI : FI field description
bits : 8 - 8 (1 bit)
RI : RI field description
bits : 9 - 9 (1 bit)
DIR : DIR field description
bits : 10 - 10 (1 bit)
PRI : PRI field description
bits : 12 - 13 (2 bit)
TSIZE : TSIZE field description
bits : 16 - 27 (12 bit)
Channel 0 Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
HTIE : HTIE field description
bits : 1 - 1 (1 bit)
FTIE : FTIE field description
bits : 2 - 2 (1 bit)
CIRC : CIRC field description
bits : 3 - 3 (1 bit)
BDW : BDW field description
bits : 4 - 5 (2 bit)
DIR : DIR field description
bits : 6 - 6 (1 bit)
SSEL : SSEL field description
bits : 8 - 10 (3 bit)
INC : INC field description
bits : 11 - 11 (1 bit)
PRI : PRI field description
bits : 12 - 13 (2 bit)
TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)
Channel 7 Flash Address Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSAD : FLSAD field description
bits : 0 - 14 (15 bit)
Channel 7 RAM Address Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMAD : RAMAD field description
bits : 0 - 11 (12 bit)
DMA Interrupt Status Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHHT : CHHT field description
bits : 0 - 7 (8 bit)
CHFT : CHFT field description
bits : 8 - 15 (8 bit)
ADDRERR : ADDRERR field description
bits : 16 - 16 (1 bit)
Channel 0 Memory Address Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)
Channel 1 Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN field description
bits : 0 - 0 (1 bit)
HTIE : HTIE field description
bits : 1 - 1 (1 bit)
FTIE : FTIE field description
bits : 2 - 2 (1 bit)
CIRC : CIRC field description
bits : 3 - 3 (1 bit)
BDW : BDW field description
bits : 4 - 5 (2 bit)
DIR : DIR field description
bits : 6 - 6 (1 bit)
SSEL : SSEL field description
bits : 8 - 10 (3 bit)
INC : INC field description
bits : 11 - 11 (1 bit)
PRI : PRI field description
bits : 12 - 13 (2 bit)
TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.