\n

DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection :

Registers

GCR

CH1MAD

CH2CR

CH2MAD

CH3CR

CH3MAD

CH4CR

CH4MAD

CH5CR

CH5MAD

CH6CR

CH6MAD

CH7CR

CH0CR

CH7FLSAD

CH7RAMAD

ISR

CH0MAD

CH1CR


GCR

DMA Global Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCR GCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN ADDRERR_EN

EN : EN field description
bits : 0 - 0 (1 bit)

ADDRERR_EN : ADDRERR_EN field description
bits : 1 - 1 (1 bit)


CH1MAD

Channel 1 Memory Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1MAD CH1MAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMAD

MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)


CH2CR

Channel 2 Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2CR CH2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HTIE FTIE CIRC BDW DIR SSEL INC PRI TSIZE

EN : EN field description
bits : 0 - 0 (1 bit)

HTIE : HTIE field description
bits : 1 - 1 (1 bit)

FTIE : FTIE field description
bits : 2 - 2 (1 bit)

CIRC : CIRC field description
bits : 3 - 3 (1 bit)

BDW : BDW field description
bits : 4 - 5 (2 bit)

DIR : DIR field description
bits : 6 - 6 (1 bit)

SSEL : SSEL field description
bits : 8 - 10 (3 bit)

INC : INC field description
bits : 11 - 11 (1 bit)

PRI : PRI field description
bits : 12 - 13 (2 bit)

TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)


CH2MAD

Channel 2 Memory Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2MAD CH2MAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMAD

MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)


CH3CR

Channel 3 Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3CR CH3CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HTIE FTIE CIRC BDW DIR SSEL INC PRI TSIZE

EN : EN field description
bits : 0 - 0 (1 bit)

HTIE : HTIE field description
bits : 1 - 1 (1 bit)

FTIE : FTIE field description
bits : 2 - 2 (1 bit)

CIRC : CIRC field description
bits : 3 - 3 (1 bit)

BDW : BDW field description
bits : 4 - 5 (2 bit)

DIR : DIR field description
bits : 6 - 6 (1 bit)

SSEL : SSEL field description
bits : 8 - 10 (3 bit)

INC : INC field description
bits : 11 - 11 (1 bit)

PRI : PRI field description
bits : 12 - 13 (2 bit)

TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)


CH3MAD

Channel 3 Memory Address Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3MAD CH3MAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMAD

MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)


CH4CR

Channel 4 Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4CR CH4CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HTIE FTIE CIRC BDW DIR SSEL INC PRI TSIZE

EN : EN field description
bits : 0 - 0 (1 bit)

HTIE : HTIE field description
bits : 1 - 1 (1 bit)

FTIE : FTIE field description
bits : 2 - 2 (1 bit)

CIRC : CIRC field description
bits : 3 - 3 (1 bit)

BDW : BDW field description
bits : 4 - 5 (2 bit)

DIR : DIR field description
bits : 6 - 6 (1 bit)

SSEL : SSEL field description
bits : 8 - 10 (3 bit)

INC : INC field description
bits : 11 - 11 (1 bit)

PRI : PRI field description
bits : 12 - 13 (2 bit)

TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)


CH4MAD

Channel 4 Memory Address Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4MAD CH4MAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMAD

MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)


CH5CR

Channel 5 Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5CR CH5CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HTIE FTIE CIRC BDW DIR SSEL INC PRI TSIZE

EN : EN field description
bits : 0 - 0 (1 bit)

HTIE : HTIE field description
bits : 1 - 1 (1 bit)

FTIE : FTIE field description
bits : 2 - 2 (1 bit)

CIRC : CIRC field description
bits : 3 - 3 (1 bit)

BDW : BDW field description
bits : 4 - 5 (2 bit)

DIR : DIR field description
bits : 6 - 6 (1 bit)

SSEL : SSEL field description
bits : 8 - 10 (3 bit)

INC : INC field description
bits : 11 - 11 (1 bit)

PRI : PRI field description
bits : 12 - 13 (2 bit)

TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)


CH5MAD

Channel 5 Memory Address Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5MAD CH5MAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMAD

MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)


CH6CR

Channel 6 Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6CR CH6CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HTIE FTIE CIRC BDW DIR SSEL INC PRI TSIZE

EN : EN field description
bits : 0 - 0 (1 bit)

HTIE : HTIE field description
bits : 1 - 1 (1 bit)

FTIE : FTIE field description
bits : 2 - 2 (1 bit)

CIRC : CIRC field description
bits : 3 - 3 (1 bit)

BDW : BDW field description
bits : 4 - 5 (2 bit)

DIR : DIR field description
bits : 6 - 6 (1 bit)

SSEL : SSEL field description
bits : 8 - 10 (3 bit)

INC : INC field description
bits : 11 - 11 (1 bit)

PRI : PRI field description
bits : 12 - 13 (2 bit)

TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)


CH6MAD

Channel 6 Memory Address Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6MAD CH6MAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMAD

MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)


CH7CR

Channel 7 Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7CR CH7CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HTIE FTIE FI RI DIR PRI TSIZE

EN : EN field description
bits : 0 - 0 (1 bit)

HTIE : HTIE field description
bits : 1 - 1 (1 bit)

FTIE : FTIE field description
bits : 2 - 2 (1 bit)

FI : FI field description
bits : 8 - 8 (1 bit)

RI : RI field description
bits : 9 - 9 (1 bit)

DIR : DIR field description
bits : 10 - 10 (1 bit)

PRI : PRI field description
bits : 12 - 13 (2 bit)

TSIZE : TSIZE field description
bits : 16 - 27 (12 bit)


CH0CR

Channel 0 Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CR CH0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HTIE FTIE CIRC BDW DIR SSEL INC PRI TSIZE

EN : EN field description
bits : 0 - 0 (1 bit)

HTIE : HTIE field description
bits : 1 - 1 (1 bit)

FTIE : FTIE field description
bits : 2 - 2 (1 bit)

CIRC : CIRC field description
bits : 3 - 3 (1 bit)

BDW : BDW field description
bits : 4 - 5 (2 bit)

DIR : DIR field description
bits : 6 - 6 (1 bit)

SSEL : SSEL field description
bits : 8 - 10 (3 bit)

INC : INC field description
bits : 11 - 11 (1 bit)

PRI : PRI field description
bits : 12 - 13 (2 bit)

TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)


CH7FLSAD

Channel 7 Flash Address Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7FLSAD CH7FLSAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLSAD

FLSAD : FLSAD field description
bits : 0 - 14 (15 bit)


CH7RAMAD

Channel 7 RAM Address Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7RAMAD CH7RAMAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMAD

RAMAD : RAMAD field description
bits : 0 - 11 (12 bit)


ISR

DMA Interrupt Status Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHHT CHFT ADDRERR

CHHT : CHHT field description
bits : 0 - 7 (8 bit)

CHFT : CHFT field description
bits : 8 - 15 (8 bit)

ADDRERR : ADDRERR field description
bits : 16 - 16 (1 bit)


CH0MAD

Channel 0 Memory Address Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0MAD CH0MAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMAD

MEMAD : MEMAD field description
bits : 0 - 31 (32 bit)


CH1CR

Channel 1 Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CR CH1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN HTIE FTIE CIRC BDW DIR SSEL INC PRI TSIZE

EN : EN field description
bits : 0 - 0 (1 bit)

HTIE : HTIE field description
bits : 1 - 1 (1 bit)

FTIE : FTIE field description
bits : 2 - 2 (1 bit)

CIRC : CIRC field description
bits : 3 - 3 (1 bit)

BDW : BDW field description
bits : 4 - 5 (2 bit)

DIR : DIR field description
bits : 6 - 6 (1 bit)

SSEL : SSEL field description
bits : 8 - 10 (3 bit)

INC : INC field description
bits : 11 - 11 (1 bit)

PRI : PRI field description
bits : 12 - 13 (2 bit)

TSIZE : TSIZE field description
bits : 16 - 31 (16 bit)



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