\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :
CRC Data Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR : DR field description
bits : 0 - 31 (32 bit)
CRC Polynominal Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POLY : POLY field description
bits : 0 - 31 (32 bit)
CRC Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : SEL field description
bits : 0 - 1 (2 bit)
access : read-write
XOR : XOR field description
bits : 2 - 2 (1 bit)
access : read-write
BUSY : BUSY field description
bits : 3 - 3 (1 bit)
access : read-only
RES : RES field description
bits : 4 - 4 (1 bit)
access : read-only
RFLTO : RFLTO field description
bits : 5 - 5 (1 bit)
access : read-write
RFLTIN : RFLTIN field description
bits : 6 - 7 (2 bit)
access : read-write
PARA : PARA field description
bits : 8 - 8 (1 bit)
access : read-write
OPWD : OPWD field description
bits : 9 - 9 (1 bit)
access : read-write
CRC Linear Feedback Shift Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LFSR : LFSR field description
bits : 0 - 31 (32 bit)
CRC output XOR Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XOR : XOR field description
bits : 0 - 31 (32 bit)
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