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LPTIM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :

Registers

CFGR

IER

ISR

CR

CCR1

CCR2

CNT

CCSR

ARR


CFGR

LPTIM Config Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMOD ONST TRIGCFG EDGESEL DIVSEL LPTINSEL PSCSEL ETR_AFEN

TMOD : TMOD field description
bits : 0 - 1 (2 bit)

ONST : ONST field description
bits : 2 - 2 (1 bit)

TRIGCFG : TRIGCFG field description
bits : 5 - 6 (2 bit)

EDGESEL : EDGESEL field description
bits : 7 - 7 (1 bit)

DIVSEL : DIVSEL field description
bits : 10 - 12 (3 bit)

LPTINSEL : LPTINSEL field description
bits : 13 - 13 (1 bit)

PSCSEL : PSCSEL field description
bits : 14 - 14 (1 bit)

ETR_AFEN : ETR_AFEN field description
bits : 24 - 24 (1 bit)


IER

LPTIM Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1IE CC2IE OVIE TRIGIE OVR1IE OVR2IE

CC1IE : CC1IE field description
bits : 0 - 0 (1 bit)

CC2IE : CC2IE field description
bits : 1 - 1 (1 bit)

OVIE : OVIE field description
bits : 2 - 2 (1 bit)

TRIGIE : TRIGIE field description
bits : 3 - 3 (1 bit)

OVR1IE : OVR1IE field description
bits : 8 - 8 (1 bit)

OVR2IE : OVR2IE field description
bits : 9 - 9 (1 bit)


ISR

LPTIM Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1IF CC2IF OVIF TRIGIF CAP1OVR CAP2OVR

CC1IF : CC1IF field description
bits : 0 - 0 (1 bit)

CC2IF : CC2IF field description
bits : 1 - 1 (1 bit)

OVIF : OVIF field description
bits : 2 - 2 (1 bit)

TRIGIF : TRIGIF field description
bits : 3 - 3 (1 bit)

CAP1OVR : CAP1OVR field description
bits : 8 - 8 (1 bit)

CAP2OVR : CAP2OVR field description
bits : 9 - 9 (1 bit)


CR

LPTIM Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : EN field description
bits : 0 - 0 (1 bit)


CCR1

LPTIM Capture/Compare Register1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR1 CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR1

CCR1 : CCR1 field description
bits : 0 - 31 (32 bit)


CCR2

LPTIM Capture/Compare Register2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR2 CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR2

CCR2 : CCR2 field description
bits : 0 - 31 (32 bit)


CNT

LPTIM Counter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT32

CNT32 : CNT32 field description
bits : 0 - 31 (32 bit)


CCSR

LPTIM Capture/Compare Control and Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCSR CCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1S CC2S POLAR1 POLAR2 CAP1CFG CAP2CFG CAP1EDGE CAP2EDGE CAP1SSEL CAP2SSEL

CC1S : CC1S field description
bits : 0 - 1 (2 bit)
access : read-write

CC2S : CC2S field description
bits : 2 - 3 (2 bit)
access : read-write

POLAR1 : POLAR1 field description
bits : 4 - 4 (1 bit)
access : read-write

POLAR2 : POLAR2 field description
bits : 5 - 5 (1 bit)
access : read-write

CAP1CFG : CAP1CFG field description
bits : 8 - 9 (2 bit)
access : read-write

CAP2CFG : CAP2CFG field description
bits : 10 - 11 (2 bit)
access : read-write

CAP1EDGE : CAP1EDGE field description
bits : 12 - 12 (1 bit)
access : read-only

CAP2EDGE : CAP2EDGE field description
bits : 13 - 13 (1 bit)
access : read-only

CAP1SSEL : CAP1SSEL field description
bits : 16 - 17 (2 bit)
access : read-write

CAP2SSEL : CAP2SSEL field description
bits : 18 - 19 (2 bit)
access : read-write


ARR

LPTIM Auto-Reload Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARR ARR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR

ARR : ARR field description
bits : 0 - 31 (32 bit)



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