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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :

Registers

ISR

SMTR

CHER

DR

SAMPT

HLTR

IER

CR

CFGR


ISR

ADC Interrupt and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOC EOS OVR BUSY AWD_UL AWD_AH

EOC : EOC field description
bits : 0 - 0 (1 bit)
access : read-write

EOS : EOS field description
bits : 1 - 1 (1 bit)
access : read-write

OVR : OVR field description
bits : 2 - 2 (1 bit)
access : read-write

BUSY : BUSY field description
bits : 3 - 3 (1 bit)
access : read-only

AWD_UL : AWD_UL field description
bits : 5 - 5 (1 bit)
access : read-write

AWD_AH : AWD_AH field description
bits : 6 - 6 (1 bit)
access : read-write


SMTR

ADC Sampling Time Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMTR SMTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMTS1 SMTS2 CHCG

SMTS1 : SMTS1 field description
bits : 0 - 3 (4 bit)

SMTS2 : SMTS2 field description
bits : 4 - 7 (4 bit)

CHCG : CHCG field description
bits : 8 - 11 (4 bit)


CHER

ADC Channel Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHER CHER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECH0 ECH1 ECH2 ECH3 ECH4 ECH5 ECH6 ECH7 ECH8 ECH9 ECH10 ECH11 TSCH REFCH OPA1CH OPA2CH

ECH0 : ECH0 field description
bits : 0 - 0 (1 bit)

ECH1 : ECH1 field description
bits : 1 - 1 (1 bit)

ECH2 : ECH2 field description
bits : 2 - 2 (1 bit)

ECH3 : ECH3 field description
bits : 3 - 3 (1 bit)

ECH4 : ECH4 field description
bits : 4 - 4 (1 bit)

ECH5 : ECH5 field description
bits : 5 - 5 (1 bit)

ECH6 : ECH6 field description
bits : 6 - 6 (1 bit)

ECH7 : ECH7 field description
bits : 7 - 7 (1 bit)

ECH8 : ECH8 field description
bits : 8 - 8 (1 bit)

ECH9 : ECH9 field description
bits : 9 - 9 (1 bit)

ECH10 : ECH10 field description
bits : 10 - 10 (1 bit)

ECH11 : ECH11 field description
bits : 11 - 11 (1 bit)

TSCH : TSCH field description
bits : 16 - 16 (1 bit)

REFCH : REFCH field description
bits : 17 - 17 (1 bit)

OPA1CH : OPA1CH field description
bits : 18 - 18 (1 bit)

OPA2CH : OPA2CH field description
bits : 19 - 19 (1 bit)


DR

ADC Data Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DR DR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA field description
bits : 0 - 15 (16 bit)


SAMPT

ADC Sampling Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAMPT SAMPT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMPT_S

SAMPT_S : SAMPT_S field description
bits : 0 - 0 (1 bit)


HLTR

ADC analog watchdog Threshold Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HLTR HLTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AWD_LT AWD_HT

AWD_LT : AWD_LT field description
bits : 0 - 11 (12 bit)

AWD_HT : AWD_HT field description
bits : 16 - 27 (12 bit)


IER

ADC Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOCIE EOSIE OVRIE AWD_ULIE AWD_AHIE

EOCIE : EOCIE field description
bits : 0 - 0 (1 bit)

EOSIE : EOSIE field description
bits : 1 - 1 (1 bit)

OVRIE : OVRIE field description
bits : 2 - 2 (1 bit)

AWD_ULIE : AWD_ULIE field description
bits : 5 - 5 (1 bit)

AWD_AHIE : AWD_AHIE field description
bits : 6 - 6 (1 bit)


CR

ADC Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADEN START EXSYNC EXSAMP

ADEN : ADEN field description
bits : 0 - 0 (1 bit)

START : START field description
bits : 1 - 1 (1 bit)

EXSYNC : EXSYNC field description
bits : 8 - 8 (1 bit)

EXSAMP : EXSAMP field description
bits : 9 - 9 (1 bit)


CFGR

ADC Config Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN DMACFG SCANDIR EXTS OVRM CONT WAIT SEMI TRGCFG IOTRFEN OVSEN OVSR OVSS AWDEN AWDSC AWDCH

DMAEN : DMAEN field description
bits : 0 - 0 (1 bit)

DMACFG : DMACFG field description
bits : 1 - 1 (1 bit)

SCANDIR : SCANDIR field description
bits : 2 - 2 (1 bit)

EXTS : EXTS field description
bits : 4 - 7 (4 bit)

OVRM : OVRM field description
bits : 8 - 8 (1 bit)

CONT : CONT field description
bits : 9 - 9 (1 bit)

WAIT : WAIT field description
bits : 10 - 10 (1 bit)

SEMI : SEMI field description
bits : 11 - 11 (1 bit)

TRGCFG : TRGCFG field description
bits : 12 - 13 (2 bit)

IOTRFEN : IOTRFEN field description
bits : 14 - 14 (1 bit)

OVSEN : OVSEN field description
bits : 16 - 16 (1 bit)

OVSR : OVSR field description
bits : 17 - 19 (3 bit)

OVSS : OVSS field description
bits : 20 - 23 (4 bit)

AWDEN : AWDEN field description
bits : 24 - 24 (1 bit)

AWDSC : AWDSC field description
bits : 25 - 25 (1 bit)

AWDCH : AWDCH field description
bits : 26 - 29 (4 bit)



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