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EXMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

SNCTL

SNWTCFG

SNTCFG


SNCTL

SRAM/NOR Flash control registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNCTL SNCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRBKEN NRMUX NRTP NRW NREN SBRSTEN NRWTPOL WRAPEN NRWTCFG WREN NRWTEN EXMODEN ASYNCWAIT CPS SYNCWR

NRBKEN : NOR region enable
bits : 0 - 0 (1 bit)

NRMUX : NOR region memory address/data multiplexing
bits : 1 - 1 (1 bit)

NRTP : NOR region memory type
bits : 2 - 3 (2 bit)

NRW : NOR region memory data bus width
bits : 4 - 5 (2 bit)

NREN : NOR Flash access enable
bits : 6 - 6 (1 bit)

SBRSTEN : synchronous burst enable
bits : 8 - 8 (1 bit)

NRWTPOL : NWAIT signal polarity
bits : 9 - 9 (1 bit)

WRAPEN : wrapped burst mode enable
bits : 10 - 10 (1 bit)

NRWTCFG : NWAIT signal configuration
bits : 11 - 11 (1 bit)

WREN : write enable
bits : 12 - 12 (1 bit)

NRWTEN : NWAIT signal enable
bits : 13 - 13 (1 bit)

EXMODEN : extended mode enable
bits : 14 - 14 (1 bit)

ASYNCWAIT : asynchronous wait
bits : 15 - 15 (1 bit)

CPS : CRAM page size
bits : 16 - 18 (3 bit)

SYNCWR : synchronous write
bits : 19 - 19 (1 bit)


SNWTCFG

SRAM/NOR write timing configuration registers
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNWTCFG SNWTCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WASET WAHLD WDSET WBUSLAT WASYNCMOD

WASET : address setup time
bits : 0 - 3 (4 bit)

WAHLD : address hold time
bits : 4 - 7 (4 bit)

WDSET : data setup time
bits : 8 - 15 (8 bit)

WBUSLAT : bus latency
bits : 16 - 19 (4 bit)

WASYNCMOD : asynchronous access mode
bits : 28 - 29 (2 bit)


SNTCFG

SRAM/NOR Flash timing configuration registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNTCFG SNTCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASET AHLD DSET BUSLAT CKDIV DLAT ASYNCMOD

ASET : address setup time
bits : 0 - 3 (4 bit)

AHLD : address hold time
bits : 4 - 7 (4 bit)

DSET : data setup time
bits : 8 - 15 (8 bit)

BUSLAT : bus latency
bits : 16 - 19 (4 bit)

CKDIV : synchronous clock divide ratio
bits : 20 - 23 (4 bit)

DLAT : data latency for NOR Flash
bits : 24 - 27 (4 bit)

ASYNCMOD : asynchronous access mode
bits : 28 - 29 (2 bit)



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