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ENET

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

MAC_CFG

MAC_PHY_CTL

MAC_PHY_DATA

MAC_FCTL

MAC_VLT

MAC_RWFF

MAC_WUM

MAC_INTF

MAC_INTMSK

MAC_FRMF

MAC_ADDR0H

MAC_ADDR0L

MAC_ADDR1H

MAC_ADDR1L

MAC_ADDR2H

MAC_ADDR2L

MAC_ADDR3H

MAC_ADDR3L

MAC_HLH

MAC_HLL


MAC_CFG

Ethernet MAC configuration register (MAC_CFG)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_CFG MAC_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REN TEN DFC BOL APCD RTD IPFCO DPM LBM ROD SPD CSD IGBS JBD WDD

REN : Receiver enable
bits : 2 - 2 (1 bit)

TEN : Transmitter enable
bits : 3 - 3 (1 bit)

DFC : Deferral check
bits : 4 - 4 (1 bit)

BOL : Back-off limit
bits : 5 - 6 (2 bit)

APCD : Automatic pad/CRC drop
bits : 7 - 7 (1 bit)

RTD : Retry disable
bits : 9 - 9 (1 bit)

IPFCO : IP frame checksum offload
bits : 10 - 10 (1 bit)

DPM : Duplex mode
bits : 11 - 11 (1 bit)

LBM : Loopback mode
bits : 12 - 12 (1 bit)

ROD : Receive own disable
bits : 13 - 13 (1 bit)

SPD : Fast Ethernet speed
bits : 14 - 14 (1 bit)

CSD : Carrier sense disable
bits : 16 - 16 (1 bit)

IGBS : Inter frame gap bit selection
bits : 17 - 19 (3 bit)

JBD : Jabber disable
bits : 22 - 22 (1 bit)

WDD : Watchdog disable
bits : 23 - 23 (1 bit)


MAC_PHY_CTL

Ethernet MAC PHY control register (MAC_PHY_CTL)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_PHY_CTL MAC_PHY_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB PW CLR PR PA

PB : PHY busy
bits : 0 - 0 (1 bit)

PW : PHY write
bits : 1 - 1 (1 bit)

CLR : Clock range
bits : 2 - 4 (3 bit)

PR : PHY register
bits : 6 - 10 (5 bit)

PA : PHY address
bits : 11 - 15 (5 bit)


MAC_PHY_DATA

Ethernet MAC MII data register (MAC_PHY_DATA)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_PHY_DATA MAC_PHY_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD

PD : PHY data
bits : 0 - 15 (16 bit)


MAC_FCTL

Ethernet MAC flow control register (MAC_FCTL)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_FCTL MAC_FCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLCB_BKPA TFCEN RFCEN UPFDT PLTS DZQP PTM

FLCB_BKPA : Flow control busy/back pressure activate
bits : 0 - 0 (1 bit)

TFCEN : Transmit flow control enable
bits : 1 - 1 (1 bit)

RFCEN : Receive flow control enable
bits : 2 - 2 (1 bit)

UPFDT : Unicast pause frame detect
bits : 3 - 3 (1 bit)

PLTS : Pause low threshold
bits : 4 - 5 (2 bit)

DZQP : Disable Zero-quanta pause
bits : 7 - 7 (1 bit)

PTM : Pause time
bits : 16 - 31 (16 bit)


MAC_VLT

Ethernet MAC VLAN tag register (MAC_VLT)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_VLT MAC_VLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLTI VLTC

VLTI : VLAN tag identifier (for receive frames)
bits : 0 - 15 (16 bit)

VLTC : 12-bit VLAN tag comparison
bits : 16 - 16 (1 bit)


MAC_RWFF

Ethernet MAC remote wakeup frame filter register (MAC_RWFF)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_RWFF MAC_RWFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MAC_WUM

Ethernet MAC wakeup management register (MAC_WUM)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_WUM MAC_WUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWD MPEN WFEN MPKR WUFR GU WUFFRPR

PWD : Power down
bits : 0 - 0 (1 bit)

MPEN : Magic Packet enable
bits : 1 - 1 (1 bit)

WFEN : Wakeup frame enable
bits : 2 - 2 (1 bit)

MPKR : Magic packet received
bits : 5 - 5 (1 bit)

WUFR : Wakeup frame received
bits : 6 - 6 (1 bit)

GU : Global unicast
bits : 9 - 9 (1 bit)

WUFFRPR : Wakeup frame filter register pointer reset
bits : 31 - 31 (1 bit)


MAC_INTF

Ethernet MAC interrupt flag register (MAC_INTF)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MAC_INTF MAC_INTF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUM MSC MSCR MSCT TMST

WUM : WUM status
bits : 3 - 3 (1 bit)

MSC : MSC status
bits : 4 - 4 (1 bit)

MSCR : MSC receive status
bits : 5 - 5 (1 bit)

MSCT : MSC transmit status
bits : 6 - 6 (1 bit)

TMST : Time stamp trigger status
bits : 9 - 9 (1 bit)


MAC_INTMSK

Ethernet MAC interrupt mask register (MAC_INTMSK)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_INTMSK MAC_INTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUMIM TMSTIM

WUMIM : WUM interrupt mask
bits : 3 - 3 (1 bit)

TMSTIM : Time stamp trigger interrupt mask
bits : 9 - 9 (1 bit)


MAC_FRMF

Ethernet MAC frame filter register (MAC_FRMF)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_FRMF MAC_FRMF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PM HUF HMF DAIFLT MFD BFRMD PCFRM SAIFLT SAFLT HPFLT FAR

PM : Promiscuous mode
bits : 0 - 0 (1 bit)

HUF : Hash unicast filter
bits : 1 - 1 (1 bit)

HMF : Hash multicast filter
bits : 2 - 2 (1 bit)

DAIFLT : Destination address inverse filtering
bits : 3 - 3 (1 bit)

MFD : multicast filter disable
bits : 4 - 4 (1 bit)

BFRMD : Broadcast frames disable
bits : 5 - 5 (1 bit)

PCFRM : Pass control frames
bits : 6 - 7 (2 bit)

SAIFLT : Source address inverse filtering
bits : 8 - 8 (1 bit)

SAFLT : Source address filter
bits : 9 - 9 (1 bit)

HPFLT : Hash or perfect filter
bits : 10 - 10 (1 bit)

FAR : Frames all receive
bits : 31 - 31 (1 bit)


MAC_ADDR0H

Ethernet MAC address 0 high register (MAC_ADDR0H)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_ADDR0H MAC_ADDR0H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR0H MO

ADDR0H : MAC address0 high
bits : 0 - 15 (16 bit)
access : read-write

MO : Always 1
bits : 31 - 31 (1 bit)
access : read-write


MAC_ADDR0L

Ethernet MAC address 0 low register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_ADDR0L MAC_ADDR0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR0L

ADDR0L : MAC address0 low
bits : 0 - 31 (32 bit)


MAC_ADDR1H

Ethernet MAC address 1 high register (MAC_ADDR1H)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_ADDR1H MAC_ADDR1H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR1H MB SAF AFE

ADDR1H : MAC address1 high
bits : 0 - 15 (16 bit)

MB : Mask byte
bits : 24 - 29 (6 bit)

SAF : Source address filter
bits : 30 - 30 (1 bit)

AFE : Address filter enable
bits : 31 - 31 (1 bit)


MAC_ADDR1L

Ethernet MAC address1 low register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_ADDR1L MAC_ADDR1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR1L

ADDR1L : MAC address1 low
bits : 0 - 31 (32 bit)


MAC_ADDR2H

Ethernet MAC address 2 high register (MAC_ADDR2H)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_ADDR2H MAC_ADDR2H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR2H MB SAF AFE

ADDR2H : Ethernet MAC address 2 high register
bits : 0 - 15 (16 bit)

MB : Mask byte
bits : 24 - 29 (6 bit)

SAF : Source address filter
bits : 30 - 30 (1 bit)

AFE : Address filter enable
bits : 31 - 31 (1 bit)


MAC_ADDR2L

Ethernet MAC address 2 low register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_ADDR2L MAC_ADDR2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR2L

ADDR2L : MAC address2 low
bits : 0 - 31 (32 bit)


MAC_ADDR3H

Ethernet MAC address 3 high register (MAC_ADDR3H)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_ADDR3H MAC_ADDR3H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR3H MB SAF AFE

ADDR3H : MAC address3 high
bits : 0 - 15 (16 bit)

MB : Mask byte
bits : 24 - 29 (6 bit)

SAF : Source address filter
bits : 30 - 30 (1 bit)

AFE : Address filter enable
bits : 31 - 31 (1 bit)


MAC_ADDR3L

Ethernet MAC address 3 low register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_ADDR3L MAC_ADDR3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR3L

ADDR3L : MAC address3 low
bits : 0 - 31 (32 bit)


MAC_HLH

Ethernet MAC hash list high register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_HLH MAC_HLH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLH

HLH : Hash list high
bits : 0 - 31 (32 bit)


MAC_HLL

Ethernet MAC hash list low register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC_HLL MAC_HLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HLL

HLL : Hash list low
bits : 0 - 31 (32 bit)



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