\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Ethernet MSC control register (MSC_CTL)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTR : Counter reset
bits : 0 - 0 (1 bit)
CTSR : Counter stop rollover
bits : 1 - 1 (1 bit)
RTOR : Reset on read
bits : 2 - 2 (1 bit)
MCFZ : MSC counter freeze
bits : 3 - 3 (1 bit)
Ethernet MSC transmit interrupt mask register (MSC_TINTMSK)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TGFSCIM : Transmitted good frames single collision interrupt mask
bits : 14 - 14 (1 bit)
TGFMSCIM : Transmitted good frames more single interrupt collision mask
bits : 15 - 15 (1 bit)
TGFIM : Transmitted good frames interrupt mask
bits : 21 - 21 (1 bit)
Ethernet MSC receive interrupt flag register (MSC_RINTF)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFCE : Received frames CRC error
bits : 5 - 5 (1 bit)
RFAE : Received frames alignment error
bits : 6 - 6 (1 bit)
RGUF : Received Good Unicast Frames
bits : 17 - 17 (1 bit)
Ethernet MSC transmitted good frames after a single collision counter
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SCC : Transmitted good frames after a single collision counter
bits : 0 - 31 (32 bit)
Ethernet MSC transmitted good frames after more than a single collision
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MSCC : Transmitted good frames after more than a single collision counter
bits : 0 - 31 (32 bit)
Ethernet MSC transmitted good frames counter register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TGF : Transmitted good frames counter
bits : 0 - 31 (32 bit)
Ethernet MSC transmit interrupt flag register (MSC_TINTF)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TGFSC : Transmitted good frames single collision
bits : 14 - 14 (1 bit)
TGFMSC : Transmitted good frames more single collision
bits : 15 - 15 (1 bit)
TGF : Transmitted good frames
bits : 21 - 21 (1 bit)
Ethernet MSC received frames with CRC error counter register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFCER : Received frames with CRC error counter
bits : 0 - 31 (32 bit)
Ethernet MSC received frames with alignment error counter register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RFAER : Received frames with alignment error counter
bits : 0 - 31 (32 bit)
Ethernet MSC receive interrupt mask register (MSC_RINTMSK)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFCEIM : Received frame CRC error interrupt mask
bits : 5 - 5 (1 bit)
RFAEIM : Received frames alignment error interrupt mask
bits : 6 - 6 (1 bit)
RGUFIM : Received good unicast frames interrupt mask
bits : 17 - 17 (1 bit)
MSC received good unicast frames counter register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RGUF : Received good unicast frames counter
bits : 0 - 31 (32 bit)
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