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ENET

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

MSC_CTL

MSC_TINTMSK

MSC_RINTF

MSC_SCCNT

MSC_MSCCNT

MSC_TGFCNT

MSC_TINTF

MSC_RFCECNT

MSC_RFAECNT

MSC_RINTMSK

MSC_RGUFCNT


MSC_CTL

Ethernet MSC control register (MSC_CTL)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSC_CTL MSC_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTR CTSR RTOR MCFZ

CTR : Counter reset
bits : 0 - 0 (1 bit)

CTSR : Counter stop rollover
bits : 1 - 1 (1 bit)

RTOR : Reset on read
bits : 2 - 2 (1 bit)

MCFZ : MSC counter freeze
bits : 3 - 3 (1 bit)


MSC_TINTMSK

Ethernet MSC transmit interrupt mask register (MSC_TINTMSK)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSC_TINTMSK MSC_TINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TGFSCIM TGFMSCIM TGFIM

TGFSCIM : Transmitted good frames single collision interrupt mask
bits : 14 - 14 (1 bit)

TGFMSCIM : Transmitted good frames more single interrupt collision mask
bits : 15 - 15 (1 bit)

TGFIM : Transmitted good frames interrupt mask
bits : 21 - 21 (1 bit)


MSC_RINTF

Ethernet MSC receive interrupt flag register (MSC_RINTF)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSC_RINTF MSC_RINTF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFCE RFAE RGUF

RFCE : Received frames CRC error
bits : 5 - 5 (1 bit)

RFAE : Received frames alignment error
bits : 6 - 6 (1 bit)

RGUF : Received Good Unicast Frames
bits : 17 - 17 (1 bit)


MSC_SCCNT

Ethernet MSC transmitted good frames after a single collision counter
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSC_SCCNT MSC_SCCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCC

SCC : Transmitted good frames after a single collision counter
bits : 0 - 31 (32 bit)


MSC_MSCCNT

Ethernet MSC transmitted good frames after more than a single collision
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSC_MSCCNT MSC_MSCCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSCC

MSCC : Transmitted good frames after more than a single collision counter
bits : 0 - 31 (32 bit)


MSC_TGFCNT

Ethernet MSC transmitted good frames counter register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSC_TGFCNT MSC_TGFCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TGF

TGF : Transmitted good frames counter
bits : 0 - 31 (32 bit)


MSC_TINTF

Ethernet MSC transmit interrupt flag register (MSC_TINTF)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSC_TINTF MSC_TINTF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TGFSC TGFMSC TGF

TGFSC : Transmitted good frames single collision
bits : 14 - 14 (1 bit)

TGFMSC : Transmitted good frames more single collision
bits : 15 - 15 (1 bit)

TGF : Transmitted good frames
bits : 21 - 21 (1 bit)


MSC_RFCECNT

Ethernet MSC received frames with CRC error counter register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSC_RFCECNT MSC_RFCECNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFCER

RFCER : Received frames with CRC error counter
bits : 0 - 31 (32 bit)


MSC_RFAECNT

Ethernet MSC received frames with alignment error counter register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSC_RFAECNT MSC_RFAECNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFAER

RFAER : Received frames with alignment error counter
bits : 0 - 31 (32 bit)


MSC_RINTMSK

Ethernet MSC receive interrupt mask register (MSC_RINTMSK)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSC_RINTMSK MSC_RINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFCEIM RFAEIM RGUFIM

RFCEIM : Received frame CRC error interrupt mask
bits : 5 - 5 (1 bit)

RFAEIM : Received frames alignment error interrupt mask
bits : 6 - 6 (1 bit)

RGUFIM : Received good unicast frames interrupt mask
bits : 17 - 17 (1 bit)


MSC_RGUFCNT

MSC received good unicast frames counter register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MSC_RGUFCNT MSC_RGUFCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RGUF

RGUF : Received good unicast frames counter
bits : 0 - 31 (32 bit)



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