\n
address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection :
Ethernet DMA bus control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWR : Software reset
bits : 0 - 0 (1 bit)
DAB : DMA Arbitration
bits : 1 - 1 (1 bit)
DPSL : Descriptor skip length
bits : 2 - 6 (5 bit)
PGBL : Programmable burst length
bits : 8 - 13 (6 bit)
RTPR : RxDMA and TxDMA transfer priority ratio
bits : 14 - 15 (2 bit)
FB : Fixed burst
bits : 16 - 16 (1 bit)
RXDP : Rx DMA PGBL
bits : 17 - 22 (6 bit)
UIP : Use independent PGBL
bits : 23 - 23 (1 bit)
FPBL : Four times PGBL mode
bits : 24 - 24 (1 bit)
AA : Address-aligned
bits : 25 - 25 (1 bit)
Ethernet DMA transmit descriptor table address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STT : Start address of transmit table
bits : 0 - 31 (32 bit)
Ethernet DMA status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TS : Transmit status
bits : 0 - 0 (1 bit)
access : read-write
TPS : Transmit process stopped status
bits : 1 - 1 (1 bit)
access : read-write
TBU : Transmit buffer unavailable status
bits : 2 - 2 (1 bit)
access : read-write
TJT : Transmit jabber timeout status
bits : 3 - 3 (1 bit)
access : read-write
RO : Receive overflow status
bits : 4 - 4 (1 bit)
access : read-write
TU : Transmit underflow status
bits : 5 - 5 (1 bit)
access : read-write
RS : Receive status
bits : 6 - 6 (1 bit)
access : read-write
RBU : Receive buffer unavailable status
bits : 7 - 7 (1 bit)
access : read-write
RPS : Receive process stopped status
bits : 8 - 8 (1 bit)
access : read-write
RWT : Receive watchdog timeout status
bits : 9 - 9 (1 bit)
access : read-write
ET : Early transmit status
bits : 10 - 10 (1 bit)
access : read-write
FBE : Fatal bus error status
bits : 13 - 13 (1 bit)
access : read-write
ER : Early receive status
bits : 14 - 14 (1 bit)
access : read-write
AI : Abnormal interrupt summary
bits : 15 - 15 (1 bit)
access : read-write
NI : Normal interrupt summary
bits : 16 - 16 (1 bit)
access : read-write
RP : Receive process state
bits : 17 - 19 (3 bit)
access : read-only
TP : Transmit process state
bits : 20 - 22 (3 bit)
access : read-only
EB : Error bits status
bits : 23 - 25 (3 bit)
access : read-only
MSC : MSC status
bits : 27 - 27 (1 bit)
access : read-only
WUM : WUM status
bits : 28 - 28 (1 bit)
access : read-only
TST : Time stamp trigger status
bits : 29 - 29 (1 bit)
access : read-only
Ethernet DMA control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRE : Start/stop receive enable
bits : 1 - 1 (1 bit)
OSF : Operate on second frame
bits : 2 - 2 (1 bit)
RTHC : Receive threshold control
bits : 3 - 4 (2 bit)
FUF : Forward undersized good frames
bits : 6 - 6 (1 bit)
FERF : Forward error frames
bits : 7 - 7 (1 bit)
STE : Start/stop transmission enable
bits : 13 - 13 (1 bit)
TTHC : Transmit threshold control
bits : 14 - 16 (3 bit)
FTF : Flush transmit FIFO
bits : 20 - 20 (1 bit)
TSFD : Transmit Store-and-Forward
bits : 21 - 21 (1 bit)
DAFRF : Disable flushing of received frames
bits : 24 - 24 (1 bit)
RSFD : Receive Store-and-Forward
bits : 25 - 25 (1 bit)
DTCERFD : Dropping of TCP/IP checksum error frames disable
bits : 26 - 26 (1 bit)
Ethernet DMA interrupt enable register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE : Transmit interrupt enable
bits : 0 - 0 (1 bit)
TPSIE : Transmit process stopped interrupt enable
bits : 1 - 1 (1 bit)
TBUIE : Transmit buffer unavailable interrupt enable
bits : 2 - 2 (1 bit)
TJTIE : Transmit jabber timeout interrupt enable
bits : 3 - 3 (1 bit)
ROIE : Receive overflow interrupt enable
bits : 4 - 4 (1 bit)
TUIE : Transmit underflow interrupt enable
bits : 5 - 5 (1 bit)
RIE : Receive interrupt enable
bits : 6 - 6 (1 bit)
RBUIE : Receive buffer unavailable interrupt enable
bits : 7 - 7 (1 bit)
RPSIE : Receive process stopped interrupt enable
bits : 8 - 8 (1 bit)
RWTIE : receive watchdog timeout interrupt enable
bits : 9 - 9 (1 bit)
ETIE : Early transmit interrupt enable
bits : 10 - 10 (1 bit)
FBEIE : Fatal bus error interrupt enable
bits : 13 - 13 (1 bit)
ERIE : Early receive interrupt enable
bits : 14 - 14 (1 bit)
AIE : Abnormal interrupt summary enable
bits : 15 - 15 (1 bit)
NIE : Normal interrupt summary enable
bits : 16 - 16 (1 bit)
Ethernet DMA missed frame and buffer overflow counter register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MSFC : Missed frames by the controller
bits : 0 - 15 (16 bit)
OBMFC : Overflow bit for missed frame counter
bits : 16 - 16 (1 bit)
MSFA : Missed frames by the application
bits : 17 - 27 (11 bit)
OBFOC : Overflow bit for FIFO overflow counter bit
bits : 28 - 28 (1 bit)
Ethernet DMA transmit poll enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPE : Transmit poll enable
bits : 0 - 31 (32 bit)
DMA current transmit descriptor address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TDAP : transmit descriptor address pointer
bits : 0 - 31 (32 bit)
Ethernet DMA current receive descriptor address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDAP : Receive descriptor address pointer
bits : 0 - 31 (32 bit)
Ethernet DMA current transmit buffer address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TBAP : Transmit buffer address pointer
bits : 0 - 31 (32 bit)
Ethernet DMA current receive buffer address register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RBAP : receive buffer address pointer
bits : 0 - 31 (32 bit)
Ethernet DMA receive poll enable register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPE : Receive poll enable
bits : 0 - 31 (32 bit)
Ethernet DMA receive descriptor table address register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRT : Start address of receive table
bits : 0 - 31 (32 bit)
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