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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

STAT

SAMPT1

IOFF0

IOFF1

IOFF2

IOFF3

WDHT

WDLT

RSQ0

RSQ1

RSQ2

ISQ

IDATA0

CTL0

IDATA1

IDATA2

IDATA3

RDATA

CTL1

SAMPT0


STAT

status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDE EOC EOIC STIC STRC

WDE : Analog watchdog event flag
bits : 0 - 0 (1 bit)

EOC : End of group conversion flag
bits : 1 - 1 (1 bit)

EOIC : End of inserted group conversion flag
bits : 2 - 2 (1 bit)

STIC : Start flag of inserted channel group
bits : 3 - 3 (1 bit)

STRC : Start flag of regular channel group
bits : 4 - 4 (1 bit)


SAMPT1

Sample time register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAMPT1 SAMPT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPT0 SPT1 SPT2 SPT3 SPT4 SPT5 SPT6 SPT7 SPT8 SPT9

SPT0 : Channel 0 sample time selection
bits : 0 - 2 (3 bit)

SPT1 : Channel 1 sample time selection
bits : 3 - 5 (3 bit)

SPT2 : Channel 2 sample time selection
bits : 6 - 8 (3 bit)

SPT3 : Channel 3 sample time selection
bits : 9 - 11 (3 bit)

SPT4 : Channel 4 sample time selection
bits : 12 - 14 (3 bit)

SPT5 : Channel 5 sample time selection
bits : 15 - 17 (3 bit)

SPT6 : Channel 6 sample time selection
bits : 18 - 20 (3 bit)

SPT7 : Channel 7 sample time selection
bits : 21 - 23 (3 bit)

SPT8 : Channel 8 sample time selection
bits : 24 - 26 (3 bit)

SPT9 : Channel 9 sample time selection
bits : 27 - 29 (3 bit)


IOFF0

Inserted channel data offset register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFF0 IOFF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOFF

IOFF : Data offset for inserted channel 0
bits : 0 - 11 (12 bit)


IOFF1

Inserted channel data offset register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFF1 IOFF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOFF

IOFF : Data offset for inserted channel 1
bits : 0 - 11 (12 bit)


IOFF2

Inserted channel data offset register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFF2 IOFF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOFF

IOFF : Data offset for inserted channel 2
bits : 0 - 11 (12 bit)


IOFF3

Inserted channel data offset register 3
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOFF3 IOFF3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOFF

IOFF : Data offset for inserted channel 3
bits : 0 - 11 (12 bit)


WDHT

watchdog higher threshold register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDHT WDHT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDHT

WDHT : Analog watchdog higher threshold
bits : 0 - 11 (12 bit)


WDLT

watchdog lower threshold register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDLT WDLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDLT

WDLT : Analog watchdog lower threshold
bits : 0 - 11 (12 bit)


RSQ0

regular sequence register 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSQ0 RSQ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSQ12 RSQ13 RSQ14 RSQ15 RL

RSQ12 : 13th conversion in regular sequence
bits : 0 - 4 (5 bit)

RSQ13 : 14th conversion in regular sequence
bits : 5 - 9 (5 bit)

RSQ14 : 15th conversion in regular sequence
bits : 10 - 14 (5 bit)

RSQ15 : 16th conversion in regular sequence
bits : 15 - 19 (5 bit)

RL : Regular channel group length
bits : 20 - 23 (4 bit)


RSQ1

regular sequence register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSQ1 RSQ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSQ6 RSQ7 RSQ8 RSQ9 RSQ10 RSQ11

RSQ6 : 7th conversion in regular sequence
bits : 0 - 4 (5 bit)

RSQ7 : 8th conversion in regular sequence
bits : 5 - 9 (5 bit)

RSQ8 : 9th conversion in regular sequence
bits : 10 - 14 (5 bit)

RSQ9 : 10th conversion in regular sequence
bits : 15 - 19 (5 bit)

RSQ10 : 11th conversion in regular sequence
bits : 20 - 24 (5 bit)

RSQ11 : 12th conversion in regular sequence
bits : 25 - 29 (5 bit)


RSQ2

regular sequence register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSQ2 RSQ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSQ0 RSQ1 RSQ2 RSQ3 RSQ4 RSQ5

RSQ0 : 1st conversion in regular sequence
bits : 0 - 4 (5 bit)

RSQ1 : 2nd conversion in regular sequence
bits : 5 - 9 (5 bit)

RSQ2 : 3rd conversion in regular sequence
bits : 10 - 14 (5 bit)

RSQ3 : 4th conversion in regular sequence
bits : 15 - 19 (5 bit)

RSQ4 : 5th conversion in regular sequence
bits : 20 - 24 (5 bit)

RSQ5 : 6th conversion in regular sequence
bits : 25 - 29 (5 bit)


ISQ

Inserted sequence register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISQ ISQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISQ0 ISQ1 ISQ2 ISQ3 IL

ISQ0 : 1st conversion in inserted sequence
bits : 0 - 4 (5 bit)

ISQ1 : 2nd conversion in inserted sequence
bits : 5 - 9 (5 bit)

ISQ2 : 3rd conversion in inserted sequence
bits : 10 - 14 (5 bit)

ISQ3 : 4th conversion in inserted sequence
bits : 15 - 19 (5 bit)

IL : Inserted channel group length
bits : 20 - 21 (2 bit)


IDATA0

Inserted data register 0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDATA0 IDATA0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATAn

IDATAn : Inserted number n conversion data
bits : 0 - 15 (16 bit)


CTL0

control register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL0 CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDCHSEL EOCIE WDEIE EOICIE SM WDSC ICA DISRC DISIC DISNUM SYNCM IWDEN RWDEN

WDCHSEL : Analog watchdog channel select
bits : 0 - 4 (5 bit)

EOCIE : Interrupt enable for EOC
bits : 5 - 5 (1 bit)

WDEIE : Interrupt enable for WDE
bits : 6 - 6 (1 bit)

EOICIE : Interrupt enable for EOIC
bits : 7 - 7 (1 bit)

SM : Scan mode
bits : 8 - 8 (1 bit)

WDSC : When in scan mode, analog watchdog is effective on a single channel
bits : 9 - 9 (1 bit)

ICA : Inserted channel group convert automatically
bits : 10 - 10 (1 bit)

DISRC : Discontinuous mode on regular channels
bits : 11 - 11 (1 bit)

DISIC : Discontinuous mode on inserted channels
bits : 12 - 12 (1 bit)

DISNUM : Number of conversions in discontinuous mode
bits : 13 - 15 (3 bit)

SYNCM : sync mode selection
bits : 16 - 18 (3 bit)

IWDEN : Inserted channel analog watchdog enable
bits : 22 - 22 (1 bit)

RWDEN : Regular channel analog watchdog enable
bits : 23 - 23 (1 bit)


IDATA1

Inserted data register 1
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDATA1 IDATA1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATAn

IDATAn : Inserted number n conversion data
bits : 0 - 15 (16 bit)


IDATA2

Inserted data register 2
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDATA2 IDATA2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATAn

IDATAn : Inserted number n conversion data
bits : 0 - 15 (16 bit)


IDATA3

Inserted data register 3
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDATA3 IDATA3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATAn

IDATAn : Inserted number n conversion data
bits : 0 - 15 (16 bit)


RDATA

regular data register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDATA RDATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDATA

RDATA : Regular channel data
bits : 0 - 15 (16 bit)


CTL1

control register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL1 CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCON CTN CLB RSTCLB DMA DAL ETSIC ETEIC ETSRC ETERC SWICST SWRCST

ADCON : ADC on
bits : 0 - 0 (1 bit)

CTN : Continuous mode
bits : 1 - 1 (1 bit)

CLB : ADC calibration
bits : 2 - 2 (1 bit)

RSTCLB : Reset calibration
bits : 3 - 3 (1 bit)

DMA : DMA request enable
bits : 8 - 8 (1 bit)

DAL : Data alignment
bits : 11 - 11 (1 bit)

ETSIC : External trigger select for inserted channel
bits : 12 - 14 (3 bit)

ETEIC : External trigger enable for inserted channel
bits : 15 - 15 (1 bit)

ETSRC : External trigger select for regular channel
bits : 17 - 19 (3 bit)

ETERC : External trigger enable for regular channel
bits : 20 - 20 (1 bit)

SWICST : Start on inserted channel
bits : 21 - 21 (1 bit)

SWRCST : Start on regular channel
bits : 22 - 22 (1 bit)


SAMPT0

Sample time register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAMPT0 SAMPT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPT10 SPT11 SPT12 SPT13 SPT14 SPT15 SPT16 SPT17

SPT10 : Channel 10 sample time selection
bits : 0 - 2 (3 bit)

SPT11 : Channel 11 sample time selection
bits : 3 - 5 (3 bit)

SPT12 : Channel 12 sample time selection
bits : 6 - 8 (3 bit)

SPT13 : Channel 13 sample time selection
bits : 9 - 11 (3 bit)

SPT14 : Channel 14 sample time selection
bits : 12 - 14 (3 bit)

SPT15 : Channel 15 sample time selection
bits : 15 - 17 (3 bit)

SPT16 : Channel 16 sample time selection
bits : 18 - 20 (3 bit)

SPT17 : Channel 17 sample time selection
bits : 21 - 23 (3 bit)



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