\n

AFIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

EC

EXTISS2

EXTISS3

PCF1

PCF0

EXTISS0

EXTISS1


EC

Event control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EC EC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN PORT EOE

PIN : Event output pin selection
bits : 0 - 3 (4 bit)

PORT : Event output port selection
bits : 4 - 6 (3 bit)

EOE : Event output enable
bits : 7 - 7 (1 bit)


EXTISS2

EXTI sources selection register 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS2 EXTISS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8_SS EXTI9_SS EXTI10_SS EXTI11_SS

EXTI8_SS : EXTI 8 sources selection
bits : 0 - 3 (4 bit)

EXTI9_SS : EXTI 9 sources selection
bits : 4 - 7 (4 bit)

EXTI10_SS : EXTI 10 sources selection
bits : 8 - 11 (4 bit)

EXTI11_SS : EXTI 11 sources selection
bits : 12 - 15 (4 bit)


EXTISS3

EXTI sources selection register 3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS3 EXTISS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12_SS EXTI13_SS EXTI14_SS EXTI15_SS

EXTI12_SS : EXTI 12 sources selection
bits : 0 - 3 (4 bit)

EXTI13_SS : EXTI 13 sources selection
bits : 4 - 7 (4 bit)

EXTI14_SS : EXTI 14 sources selection
bits : 8 - 11 (4 bit)

EXTI15_SS : EXTI 15 sources selection
bits : 12 - 15 (4 bit)


PCF1

AFIO port configuration register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCF1 PCF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER8_REMAP TIMER9_REMAP TIMER10_REMAP TIMER12_REMAP TIMER13_REMAP FSMC_NADV

TIMER8_REMAP : TIMER8 remapping
bits : 5 - 5 (1 bit)

TIMER9_REMAP : TIMER9 remapping
bits : 6 - 6 (1 bit)

TIMER10_REMAP : TIMER10 remapping
bits : 7 - 7 (1 bit)

TIMER12_REMAP : TIMER12 remapping
bits : 8 - 8 (1 bit)

TIMER13_REMAP : TIMER13 remapping
bits : 9 - 9 (1 bit)

FSMC_NADV : FSMC_NADV connect/disconnect
bits : 10 - 10 (1 bit)


PCF0

AFIO port configuration register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCF0 PCF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0_REMAP I2C0_REMAP USART0_REMAP USART1_REMAP USART2_REMAP TIMER0_REMAP TIMER1_REMAP TIMER2_REMAP TIMER3_REMAP CAN_REMAP PD01_REMAP TIMER4CH3_IREMAP ADC0_ETRGINS_REMAP ADC0_ETRGREG_REMAP ADC1_ETRGINS_REMAP ADC1_ETRGREG_REMAP SWJ_CFG

SPI0_REMAP : SPI0 remapping
bits : 0 - 0 (1 bit)

I2C0_REMAP : I2C0 remapping
bits : 1 - 1 (1 bit)

USART0_REMAP : USART0 remapping
bits : 2 - 2 (1 bit)

USART1_REMAP : USART1 remapping
bits : 3 - 3 (1 bit)

USART2_REMAP : USART2 remapping
bits : 4 - 5 (2 bit)

TIMER0_REMAP : TIMER0 remapping
bits : 6 - 7 (2 bit)

TIMER1_REMAP : TIMER1 remapping
bits : 8 - 9 (2 bit)

TIMER2_REMAP : TIMER2 remapping
bits : 10 - 11 (2 bit)

TIMER3_REMAP : TIMER3 remapping
bits : 12 - 12 (1 bit)

CAN_REMAP : CAN alternate interface remapping
bits : 13 - 14 (2 bit)

PD01_REMAP : Port D0/Port D1 mapping on OSC_IN/OSC_OUT
bits : 15 - 15 (1 bit)

TIMER4CH3_IREMAP : TIMER4 channel3 internal remapping
bits : 16 - 16 (1 bit)

ADC0_ETRGINS_REMAP : ADC0 external trigger inserted conversion remapping
bits : 17 - 17 (1 bit)

ADC0_ETRGREG_REMAP : ADC0 external trigger regular conversion remapping
bits : 18 - 18 (1 bit)

ADC1_ETRGINS_REMAP : ADC1 external trigger inserted conversion remapping
bits : 19 - 19 (1 bit)

ADC1_ETRGREG_REMAP : ADC1 external trigger regular conversion remapping
bits : 20 - 20 (1 bit)

SWJ_CFG : Serial wire JTAG configuration
bits : 24 - 26 (3 bit)


EXTISS0

EXTI sources selection register 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS0 EXTISS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0_SS EXTI1_SS EXTI2_SS EXTI3_SS

EXTI0_SS : EXTI 0 sources selection
bits : 0 - 3 (4 bit)

EXTI1_SS : EXTI 1 sources selection
bits : 4 - 7 (4 bit)

EXTI2_SS : EXTI 2 sources selection
bits : 8 - 11 (4 bit)

EXTI3_SS : EXTI 3 sources selection
bits : 12 - 15 (4 bit)


EXTISS1

EXTI sources selection register 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTISS1 EXTISS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4_SS EXTI5_SS EXTI6_SS EXTI7_SS

EXTI4_SS : EXTI 4 sources selection
bits : 0 - 3 (4 bit)

EXTI5_SS : EXTI 5 sources selection
bits : 4 - 7 (4 bit)

EXTI6_SS : EXTI 6 sources selection
bits : 8 - 11 (4 bit)

EXTI7_SS : EXTI 7 sources selection
bits : 12 - 15 (4 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.